Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

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Date 1/07/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Optimization Overview 3. Optimizing the Design Netlist 4. Netlist Optimizations and Physical Synthesis 5. Area Optimization 6. Timing Closure and Optimization 7. Analyzing and Optimizing the Design Floorplan 8. Using the ECO Compilation Flow 9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Optimization Overview x
2.1. Device Considerations 2.2. Required Settings for Initial Compilation 2.3. Optimization Trade-Offs and Limitations 2.4. Design Visualization and Optimization Tools 2.5. Design Optimization Overview Revision History
2.1. Device Considerations x
2.1.1. Device Migration Considerations
2.2. Required Settings for Initial Compilation x
2.2.1. Initial I/O Assignment Guidelines 2.2.2. Initial Timing Constraint Guidelines
2.3. Optimization Trade-Offs and Limitations x
2.3.1. Area Reduction Trade-Offs 2.3.2. Critical Path Delay Reduction Trade-Offs 2.3.3. Power Consumption Reduction Trade-Offs 2.3.4. Compilation Time Trade-Offs
2.4. Design Visualization and Optimization Tools x
2.4.1. Design Visualization Tools 2.4.2. Design Optimization Tools
3. Optimizing the Design Netlist x
3.1. When to Use the Netlist Viewers: Analyzing Design Problems 3.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 3.3. RTL Viewer Overview 3.4. Technology Map Viewer Overview 3.5. Netlist Viewer User Interface 3.6. Schematic View 3.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 3.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 3.9. Viewing a Timing Path 3.10. Optimizing the Design Netlist Revision History
3.3. RTL Viewer Overview x
3.3.1. Maximizing Readability in RTL Viewer 3.3.2. Running the RTL Viewer
3.5. Netlist Viewer User Interface x
3.5.1. Netlist Navigator Pane 3.5.2. Properties Pane 3.5.3. Netlist Viewers Find Pane
3.6. Schematic View x
3.6.1. Display Schematics in Multiple Tabbed View 3.6.2. Schematic Symbols 3.6.3. Select Items in the Schematic View 3.6.4. Shortcut Menu Commands in the Schematic View 3.6.5. Filtering in the Schematic View 3.6.6. View Contents of Nodes in the Schematic View 3.6.7. Moving Nodes in the Schematic View 3.6.8. View LUT Representations in the Technology Map Viewer 3.6.9. Zoom Controls 3.6.10. Navigating with the Bird's Eye View 3.6.11. Partition the Schematic into Pages 3.6.12. Follow Nets Across Schematic Pages
4. Netlist Optimizations and Physical Synthesis x
4.1. Physical Synthesis Optimizations 4.2. Applying Netlist Optimizations 4.3. Scripting Support 4.4. Netlist Optimizations and Physical Synthesis Revision History
4.1. Physical Synthesis Optimizations x
4.1.1. Disabling or Enabling Physical Synthesis Optimization 4.1.2. Physical Synthesis Options
4.2. Applying Netlist Optimizations x
4.2.1. WYSIWYG Primitive Resynthesis
4.3. Scripting Support x
4.3.1. Synthesis Netlist Optimizations 4.3.2. Physical Synthesis Optimizations
5. Area Optimization x
5.1. Resource Utilization Information 5.2. Optimizing Resource Utilization 5.3. Scripting Support 5.4. Area Optimization Revision History
5.1. Resource Utilization Information x
5.1.1. Flow Summary Report 5.1.2. Fitter Reports 5.1.3. Design Assistant Recommendations 5.1.4. Analysis and Synthesis Reports 5.1.5. Compilation Messages 5.1.6. Chip Planner Visualization
5.2. Optimizing Resource Utilization x
5.2.1. Resource Utilization Issues Overview 5.2.2. I/O Pin Utilization or Placement 5.2.3. Logic Utilization or Placement 5.2.4. Routing
5.2.2. I/O Pin Utilization or Placement x
5.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package
5.2.3. Logic Utilization or Placement x
5.2.3.1. Guideline: Optimize Source Code 5.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed 5.2.3.3. Guideline: Restructure Multiplexers 5.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 5.2.3.5. Guideline: Use Register Packing 5.2.3.6. Guideline: Remove Fitter Constraints 5.2.3.7. Guideline: Flatten the Hierarchy During Synthesis 5.2.3.8. Guideline: Re-target Memory Blocks 5.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area 5.2.3.10. Guideline: Retarget or Balance DSP Blocks 5.2.3.11. Guideline: Use a Larger Device 5.2.3.12. Guideline: Reduce Global Signal Congestion 5.2.3.13. Guideline: Report Pipelining Information
5.2.4. Routing x
5.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 5.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 5.2.4.3. Guideline: Increase Router Effort Multiplier 5.2.4.4. Guideline: Remove Fitter Constraints 5.2.4.5. Guideline: Optimize Synthesis for Routability 5.2.4.6. Guideline: Optimize Source Code 5.2.4.7. Guideline: Use a Larger Device
5.3. Scripting Support x
5.3.1. Initial Compilation Settings 5.3.2. Resource Utilization Optimization Techniques
6. Timing Closure and Optimization x
6.1. Optimize Multi Corner Timing 6.2. Optimize Critical Paths 6.3. Optimize Critical Chains 6.4. Design Evaluation for Timing Closure 6.5. Timing Optimization 6.6. Periphery to Core Register Placement and Routing Optimization 6.7. Scripting Support 6.8. Timing Closure and Optimization Revision History
6.2. Optimize Critical Paths x
6.2.1. Viewing Critical Paths
6.3. Optimize Critical Chains x
6.3.1. Viewing Critical Chains
6.4. Design Evaluation for Timing Closure x
6.4.1. Review Messages 6.4.2. Evaluate Fitter Netlist Optimizations 6.4.3. Evaluate Optimization Results 6.4.4. Evaluate Resource Usage 6.4.5. Evaluate Other Reports and Adjust Settings Accordingly 6.4.6. Evaluate Clustering Difficulty 6.4.7. Revise and Recompile
6.4.4. Evaluate Resource Usage x
6.4.4.1. Evaluate Global and Non-Global Usage 6.4.4.2. Evaluate Routing Usage 6.4.4.3. Evaluate Wires Added for Hold
6.5. Timing Optimization x
6.5.1. Correct Design Assistant Rule Violations 6.5.2. Implement Fast Forward Timing Closure Recommendations 6.5.3. Review Timing Path Details 6.5.4. Try Optional Fitter Settings 6.5.5. Back-Annotate Optimized Assignments 6.5.6. Optimize Settings with Design Space Explorer II 6.5.7. I/O Timing Optimization Techniques 6.5.8. Register-to-Register Timing Optimization Techniques 6.5.9. Metastability Analysis and Optimization Techniques
6.5.2. Implement Fast Forward Timing Closure Recommendations x
6.5.2.1. Retiming Limit Details Report 6.5.2.2. Fast Forward Timing Closure Recommendations
6.5.2.1. Retiming Limit Details Report x
6.5.2.1.1. Using the Retiming Limit Details Report
6.5.2.2. Fast Forward Timing Closure Recommendations x
6.5.2.2.1. Generating Fast Forward Timing Closure Recommendations 6.5.2.2.2. Implementing Fast Forward Recommendations
6.5.3. Review Timing Path Details x
6.5.3.1. Report Timing 6.5.3.2. Report Logic Depth 6.5.3.3. Report Neighbor Paths 6.5.3.4. Report Register Spread 6.5.3.5. Report Route Net of Interest 6.5.3.6. Report Retiming Restrictions 6.5.3.7. Report Pipelining Information 6.5.3.8. Report CDC Viewer 6.5.3.9. Timing Closure Recommendations 6.5.3.10. Global Network Buffers 6.5.3.11. Resets and Global Networks 6.5.3.12. Suspicious Setup 6.5.3.13. Auto Shift Register Replacement 6.5.3.14. Clocking Architecture
6.5.3.10. Global Network Buffers x
6.5.3.10.1. Source Location 6.5.3.10.2. Insertion Delay 6.5.3.10.3. Fan-Out 6.5.3.10.4. Global Signal Assignment
6.5.4. Try Optional Fitter Settings x
6.5.4.1. Optimize Hold Timing 6.5.4.2. Fitter Aggressive Routability Optimization
6.5.6. Optimize Settings with Design Space Explorer II x
6.5.6.1. DSE II Computing Resources 6.5.6.2. DSE II Optimization Parameters 6.5.6.3. DSE II Result Management 6.5.6.4. Running DSE II
6.5.7. I/O Timing Optimization Techniques x
6.5.7.1. I/O Timing Constraints 6.5.7.2. Optimize IOC Register Placement for Timing Logic Option 6.5.7.3. Fast Input, Output, and Output Enable Registers 6.5.7.4. Programmable Delays 6.5.7.5. Use PLLs to Shift Clock Edges 6.5.7.6. Use Fast Regional Clock Networks and Regional Clocks Networks 6.5.7.7. Spine Clock Limitations
6.5.8. Register-to-Register Timing Optimization Techniques x
6.5.8.1. Optimize Source Code 6.5.8.2. Improving Register-to-Register Timing 6.5.8.3. Physical Synthesis Optimizations 6.5.8.4. Set Power Optimization During Synthesis to Normal Compilation 6.5.8.5. Optimize Synthesis for Performance, Not Area 6.5.8.6. Flatten the Hierarchy During Synthesis 6.5.8.7. Set the Synthesis Effort to High 6.5.8.8. Duplicate Registers for Fan-Out Control 6.5.8.9. Prevent Shift Register Inference 6.5.8.10. Use Other Synthesis Options Available in Your Synthesis Tool 6.5.8.11. Fitter Seed 6.5.8.12. Set Maximum Router Timing Optimization Level 6.5.8.13. Register-to-Register Timing Analysis
6.5.8.8. Duplicate Registers for Fan-Out Control x
6.5.8.8.1. Manual Register Duplication 6.5.8.8.2. Automatic Register Duplication: Estimated Physical Proximity 6.5.8.8.3. Automatic Register Duplication: Hierarchical Proximity
6.5.8.13. Register-to-Register Timing Analysis x
6.5.8.13.1. Tips for Analyzing Failing Paths 6.5.8.13.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 6.5.8.13.3. Tips for Critical Path Analysis 6.5.8.13.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 6.5.8.13.5. Global Routing Resources 6.5.8.13.6. Register RAMS and DSPs
6.6. Periphery to Core Register Placement and Routing Optimization x
6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 6.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
6.7. Scripting Support x
6.7.1. Initial Compilation Settings 6.7.2. I/O Timing Optimization Techniques 6.7.3. Register-to-Register Timing Optimization Techniques
7. Analyzing and Optimizing the Design Floorplan x
7.1. Design Floorplan Analysis in the Chip Planner 7.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner 7.3. Using Logic Lock Regions in the Chip Planner 7.4. Using User-Defined Clock Regions in the Chip Planner 7.5. Scripting Support 7.6. Analyzing and Optimizing the Design Floorplan Revision History
7.1. Design Floorplan Analysis in the Chip Planner x
7.1.1. Starting the Chip Planner 7.1.2. Chip Planner GUI Components 7.1.3. Viewing Design Elements in the Chip Planner 7.1.4. Finding Design Elements in the Chip Planner 7.1.5. Exploring Paths in the Chip Planner 7.1.6. Viewing Assignments in the Chip Planner 7.1.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner
7.1.2. Chip Planner GUI Components x
7.1.2.1. Chip Planner Toolbar 7.1.2.2. Layers Settings 7.1.2.3. Locate History Window 7.1.2.4. Chip Planner Floorplan Views
7.1.3. Viewing Design Elements in the Chip Planner x
7.1.3.1. Viewing Architecture-Specific Design Information 7.1.3.2. Viewing Available Clock Networks in the Device 7.1.3.3. Viewing Clock Sector Utilization 7.1.3.4. Viewing Routing Congestion 7.1.3.5. Viewing I/O Banks 7.1.3.6. Viewing High-Speed Serial Interfaces (HSSI) 7.1.3.7. Viewing the Source and Destination of Placed Nodes 7.1.3.8. Viewing Fan-In and Fan-Out Connections of Placed Resources 7.1.3.9. Viewing Immediate Fan-In and Fan-Out Connections 7.1.3.10. Viewing Selected Contents 7.1.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner 7.1.3.12. Viewing Module Placement by Cross-Probing to Chip Planner
7.1.4. Finding Design Elements in the Chip Planner x
7.1.4.1. Find Options (Chip Planner Search)
7.1.5. Exploring Paths in the Chip Planner x
7.1.5.1. Analyzing Connections for a Path 7.1.5.2. Locate Path from the Timing Analysis Report to the Chip Planner 7.1.5.3. Show Delays 7.1.5.4. Viewing Routing Resources
7.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner x
7.2.1. Viewing Design Connectivity and Hierarchy
7.3. Using Logic Lock Regions in the Chip Planner x
7.3.1. Viewing Connections Between Logic Lock Regions in the Chip Planner 7.3.2. Logic Lock Regions 7.3.3. Attributes of a Logic Lock Region 7.3.4. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition 7.3.5. Creating Logic Lock Regions 7.3.6. Customizing the Shape of Logic Lock Regions 7.3.7. Placing Device Resources into Logic Lock Regions 7.3.8. Hierarchical Regions 7.3.9. Additional Intel® Quartus® Prime Logic Lock Design Features 7.3.10. Logic Lock Regions Window 7.3.11. Snapping to a Region
7.3.5. Creating Logic Lock Regions x
7.3.5.1. Creating Logic Lock Regions with the Chip Planner 7.3.5.2. Creating Logic Lock Regions with the Project Navigator 7.3.5.3. Creating Logic Lock Regions with the Logic Lock Regions Window 7.3.5.4. Defining Routing Regions 7.3.5.5. Noncontiguous Logic Lock Regions 7.3.5.6. Considerations on Using Auto Sized Regions
7.3.6. Customizing the Shape of Logic Lock Regions x
7.3.6.1. Adding a New Shape to a Logic Lock Region 7.3.6.2. Subtracting Shape from Logic Lock Region 7.3.6.3. Merging Logic Lock Regions 7.3.6.4. Noncontiguous Logic Lock Regions
7.3.7. Placing Device Resources into Logic Lock Regions x
7.3.7.1. Empty Logic Lock Regions 7.3.7.2. Pin Assignment 7.3.7.3. Reserved Logic Lock Regions 7.3.7.4. Virtual Pins 7.3.7.5. Example: Placement Best Practices for Intel® Arria® 10 FPGAs
7.3.9. Additional Intel® Quartus® Prime Logic Lock Design Features x
7.3.9.1. Intel® Quartus® Prime Revisions Feature
7.4. Using User-Defined Clock Regions in the Chip Planner x
7.4.1. Creating Clock Assignments with the Chip Planner 7.4.2. Resizing a Clock Assignment 7.4.3. Moving a Clock Assignment 7.4.4. Deleting a Clock Region Assignment 7.4.5. Assigning a Clock Signal to a Clock Region 7.4.6. Clock Assignment Properties
7.5. Scripting Support x
7.5.1. Creating Logic Lock Assignments with Tcl commands 7.5.2. Assigning Virtual Pins with a Tcl command 7.5.3. Logic Lock Region Assignment Examples
8. Using the ECO Compilation Flow x
8.1. ECO Compilation Flow 8.2. ECO Tcl Script Example 8.3. Viewing ECO Compilation Reports 8.4. ECO Commands 8.5. ECO Command Limitations 8.6. Interactive ECO Fitting 8.7. Using the ECO Compilation Flow Revision History
8.4. ECO Commands x
8.4.1. ECO Command Quick Reference 8.4.2. make_connection 8.4.3. remove_connection 8.4.4. modify_lutmask 8.4.5. adjust_pll_refclk 8.4.6. modify_io_slew_rate 8.4.7. modify_io_current_strength 8.4.8. modify_io_delay_chain 8.4.9. create_new_node 8.4.10. remove_node 8.4.11. place_node 8.4.12. unplace_node 8.4.13. create_wirelut
8.6. Interactive ECO Fitting x
8.6.1. eco_load_design and eco_commit_design Commands
1. Answers to Top FAQs
2. Design Optimization Overview
3. Optimizing the Design Netlist
4. Netlist Optimizations and Physical Synthesis
5. Area Optimization
6. Timing Closure and Optimization
7. Analyzing and Optimizing the Design Floorplan
8. Using the ECO Compilation Flow
9. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Intel® Quartus® Prime Pro Edition User Guides

6.5.3.8. Report CDC Viewer

The Timing Analyzer's Reports > Clock Domain Crossings > Report CDC Viewer... command allows you to configure and display a custom clock domain crossing report and the Clock Domain Crossing (CDC) Viewer. The CDC Viewer graphically displays the setup, hold, recovery, or removal analysis of all clock transfers in your design. The equivalent scripting command is report_cdc_viewer.
Report Clock Domain Crossing Viewer Settings
Option Description
Clocks From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify.
Analysis type Options are Setup, Hold, Recovery, or Removal. The Timing Analyzer reports the results for the type of analysis you select.
Transfers Specifies the type of clock transfers to include or exclude from the report, including Timed transfers, Fully cut transfers, Clock groups, Inactive clocks, and Non-crossing transfers. You can specify the Maximum slack limit and Grid options for the report.
Detail level Full shows all details of the report and Summary filters the details and shows summary data.
Report panel name Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name, you can Overwrite or Append the file with latest data, and specify Grid or List format.
Note: In grid format reports, clocks with non-crossing transfers always appear if they have transfers between other clocks.
Tcl command Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.

You can specify the following options to customize CDC Viewer reporting:

Table 22.  CDC Viewer Report Controls
Control Description
From Clock: and To Clock: Filters the display according to the clock names you specify. Click From Clock: or To Clock: to search for specific clock names.
Legend Defines the status colors. A color coded grid displays the clock transfer status. The clock headers list each clock with transfers in the design. The GUI truncates long clock names, but you can view the full name in a tool tip or by resizing the clock header cell. The GUI represents the generated clocks as children of the parent clock. A '+' icon next to a clock name indicates the presence of generated clocks. Clicking on the clock header displays the generated clocks associated with that clock.
Toggle Data The text in each transfer cell contains data specific to each transfer. Turn on or off display of the following types of data:
  • Number of timed endpoints between clocks— the number of timed, endpoint-unique paths in the transfer. A path being “timed” means that analysis occurs on that path. Only paths with unique endpoints count towards this total.
  • Number of cut endpoints between clocks— the number of cut endpoint-unique paths, instead of timed paths. These paths are cut by either a false path or clock group assignment. Timing analysis skips such paths.
  • Worst-case slack between clocks— the worst-case slack among all endpoint-unique paths in the transfer.
  • Total negative slack between clocks— the sum of all negative slacks among all endpoint-unique paths in this transfer.
  • Tightest relationship between clocks— the lowest-value setup, hold, recovery, or removal relationship between the two clocks in this transfer.
Show Filters and Show Legend Turns on or off Filters and Legend.
Figure 43. CDC Viewer Setup Transfers Report

Each block in the grid is a transfer cell. Each transfer cell uses color and text to display important details of the paths in the transfer. The color coding represents the following states:

Table 23.  Transfer Cell Content
Cell Color Color Legend
Black Indicates no transfers. There are no paths crossing between the source and destination clock of this cell.
Green Indicates passing timing. All timing paths in this transfer, that have not been cut, meet their timing requirements.
Red Indicates failing timing. One or more of the timing paths in the transfer do not meet their timing requirements. If the transfer is between unrelated clocks, the paths likely require a synchronizer chain.
Blue Indicates clock groups. The source and destination clocks of these transfers are cut by means of asynchronous clock groups.
Gray Indicates a cut transfer. All paths in this transfer are cut by false paths. Therefore, timing analysis does not consider these paths.
Orange Indicates inactive clocks. One of the clocks in the transfer is an inactive clock (with the set_active_clocks command). The Timing Analyzer ignores such transfers.

Right-click menus allow you to perform operations on transfer cells and clock headers. When the operation is a Timing Analyzer report or SDC command, a dialog box opens containing the contents of the transfer cell.

Table 24.  Transfer Cell Right-Click Menus
Command Description
Copy Copies the contents of the transfer cell or clock header to the clipboard.
Report Timing Reports timing. Not available for transfer cells with no valid paths (gray or black cells).
Report Endpoints Reports endpoints. Not available for transfer cells with no cut paths (gray or black cells).
Report False Path Reports false paths. Not available for transfer cells with no valid paths (black cells).
Report Exceptions Reports exceptions. Only available for clock group transfers (blue cells).
Report Exceptions (with clock groups) Reports exceptions with clock groups. Only available for clock group transfers (blue cells).
Set False Path Sets a false path constraint.
Set Multicycle Path Sets a multicycle path exception.
Set Min Delay Sets a min delay constraint.
Set Max Delay Sets a max delay constraint.
Set Clock Uncertainty Sets a clock uncertainty constraint.
Table 25.  Clock Header Right-Click Menus
Command Description
Copy (include children) Copies the name of the clock header, and the names of each of its derived clocks. This option only appears for clock headers with generated clocks.
Expand/Collapse All Rows/Columns Shows or hides all derived clocks in the grid.
Create Slack Histogram Generates a slack histogram report for the clock you select.
Report Timing From/To Clock Generates a timing report for the clock you select. If you do not expand the clock to display derived clocks, the timing report includes all clocks that derive from the clock. To prevent this, expand the clock before right-clicking it.
Remove Clock(s) Removes the clock you select from the design. If you do not expand the clock, timing analysis removes all clocks that derive from the clock.

You can view CDC Viewer output in any of the following formats:

  • A report panel in the Timing Analyzer
  • Output in the Timing Analyzer Tcl console
  • A plain-text file
  • An HTML file you can view in a web browser.
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