AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.3.2. IRQ Signal

A raised IRQ signal means there is an interrupt request. IRQ goes high in Master Write, Master Read and Slave Mode if the following situation occurs.

In Master Write mode:

  • If the data byte written in the data register is successfully transferred, it gives an indication to the host to write the next byte to the data register.
  • If the acknowledgement is not received from the slave for the data transferred.
  • If arbitration is lost.
  • In the PEC set mode, if the IRQ is raised even after the STOP bit is set, it indicates that the PEC received from the slave did not match the PEC generated by the controller.

In Master Read mode:

  1. If the acknowledgement is not received from any of the slaves for the address byte transferred on the SMBDAT line.
  2. If a byte of data is received from the slave, giving an indication to the host to read the byte.
  3. If arbitration is lost.

In Slave mode (clock low stretching in Slave mode is not supported by this controller):

  • If the address received from the Master matches with the data in the address register.
  • If the reading/writing a byte of data on the SMBDAT line is completed—to give an indication to the host.
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