AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.3.3. BUSY Signal

BUSY signal indicates the following:

  • If asserted, the BUSY signal indicates that data is being transferred on the SMBDAT line.
  • If IRQ is asserted and the BUSY signal is low, it indicates that the current mode was carried out without any error.
  • When no operation is being carried out if the BUSY signal is low, it indicates that there is no activity on the SMBus (that is, the SMBus is idle).
  • If IRQ is asserted along with the BUSY signal, it indicates the failure of the current operation.

The BUSY signal goes high in Master and Slave Mode if the following situation occurs.

In Master mode:

  • An acknowledgement has not been received from the slave.
  • Arbitration is lost.
  • The host took longer than 32 microseconds (approximately) to respond after IRQ assertion.
  • PEC received in the master read mode was different from the PEC calculated by the controller.

In Slave Mode:

  • An acknowledgement has not been received in the slave write mode.
  • The host could not respond within the low period of the clock on the SMBCLK line after the IRQ was asserted.
  • STOP condition was detected on the SMBus.
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