AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller Write Cycle Read Cycle
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
Write Cycle Read Cycle 1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.3. Communicating with the SMBus Controller

Whenever the host wants to communicate with the controller, it should first read the status register to determine the present state of the controller and if necessary, write into it and then into other registers.

Write Cycle

Figure 3. Timing Diagram for Write Cycle
The following describes the write cycle:
  1. Deassert CS low.
  2. Place address of the desired register on address bus.
  3. Place data on data bus.

Read Cycle

Figure 4. Timing Diagram for Read Cycle
The following describes the read cycle:
  1. Deassert CS low.
  2. Place address of the desired register on address bus.
  3. Assert RD to read data from data bus.
Note: A read/write operation always reads/writes an entire register. Single bit operations are not possible.

Section Content
Using the Status Register
IRQ Signal
BUSY Signal

Level Two Title