AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.1. Data Transfer on SMBus

Communication between a Master and a Slave on the bus is composed of START, Slave address, Data transfer, and STOP phases.

The following are the communication phases flow:

  1. After the START phase, the Slave address is sent.
  2. Only the Slave whose address matches the address transmitted by the Master responds by sending back an acknowledge bit.
  3. When Slave addressing is achieved, the data transfer will proceed byte-by-byte.
  4. The Master can terminate the communication by generating a STOP signal to free the bus.

The bus interface logic performs the following functions:

  • Switching between Master and Slave mode
  • START/STOP signal generation
  • Packet Error Code (PEC) generation
  • R/W mode
  • Error notification

The following features are incorporated in this design example:

  • Generic and simple microcontroller interface
  • Master and Slave mode of operation
  • Arbitration lost interrupt with automatic mode switching from Master to Slave
  • PEC generation and verification in master mode
  • 98.215 KHz operation
  • Clock low extension in both Master and Slave mode
Figure 2. SMBus Data Transfer
Level Two Title