Nios® V Processor Reference Manual

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ID 683632
Date 5/26/2023
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/m Processor 3. Nios® V/g Processor 4. Nios V Processor Reference Manual Archives 5. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module
2.3.6. Interrupt Controller x
2.3.6.1. Timer and Software Interrupt Module
2.3.7. Memory and I/O Organization x
2.3.7.1. Instruction and Data Buses 2.3.7.2. Address Map
2.3.7.1. Instruction and Data Buses x
2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port
2.3.8. RISC-V based Debug Module x
2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Trigger 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/g Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Multipy and Divide Units 3.3.4. Custom Instruction 3.3.5. Reset and Debug Signals 3.3.6. Control and Status Registers 3.3.7. Exception Controller 3.3.8. Interrupt Controller 3.3.9. Memory and I/O Organization 3.3.10. RISC-V based Debug Module
3.3.8. Interrupt Controller x
3.3.8.1. Timer and Software Interrupt Module
3.3.9. Memory and I/O Organization x
3.3.9.1. Instruction and Data Buses 3.3.9.2. Address Map 3.3.9.3. Cache Memory
3.3.9.1. Instruction and Data Buses x
3.3.9.1.1. Instruction Manager Port 3.3.9.1.2. Data Manager Port
3.3.9.3. Cache Memory x
3.3.9.3.1. Instruction Cache 3.3.9.3.2. Data Cache 3.3.9.3.3. Configurable Cache Memory 3.3.9.3.4. Bypassing Cache (Peripheral Region) 3.3.9.3.5. Using Cache Memory Effectively
3.3.10. RISC-V based Debug Module x
3.3.10.1. Debug Mode 3.3.10.2. Halt from Debug Module 3.3.10.3. Trigger 3.3.10.4. Abstract Commands in Debug Mode 3.3.10.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
1. Overview
2. Nios® V/m Processor
3. Nios® V/g Processor
4. Nios V Processor Reference Manual Archives
5. Document Revision History for the Nios® V Processor Reference Manual

3.5.1. Instruction Set Reference

The Nios® V/g processor is based on the RV32IMA specification, and there are 6 types of instruction formats. They are R-type, I-type, S-type, B-type, U-type, and J-type.

Table 82.  Instruction Formats (R-type)
Bit Field (R-type)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
funct7 rs2 rs1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rs1 funct3 rd opcode
Table 83.  Instruction Formats (I-type)
Bit Field (I-type)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
imm[11:0] rs1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rs1 funct3 rd opcode
Table 84.  Instruction Formats (S-type)
Bit Field (S-type)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
imm[11:5] rs2 rs1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rs1 funct3 imm[4:0] opcode
Table 85.  Instruction Formats (B-type)
Bit Field (B-type)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
imm[12] imm[10:5] rs2 rs1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rs1 funct3 imm[4:1] imm[11] opcode
Table 86.   Instruction Formats (U-type)
Bit Field (U-type)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
imm[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
imm[15:12] rd opcode
Table 87.  Instruction Formats (J-type)
Bit Field (J-type)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
imm[20] imm[10:1] imm[11] imm[19:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
imm[15:12] rd opcode
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