Nios® V Processor Reference Manual

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ID 683632
Date 5/26/2023
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/m Processor 3. Nios® V/g Processor 4. Nios V Processor Reference Manual Archives 5. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module
2.3.6. Interrupt Controller x
2.3.6.1. Timer and Software Interrupt Module
2.3.7. Memory and I/O Organization x
2.3.7.1. Instruction and Data Buses 2.3.7.2. Address Map
2.3.7.1. Instruction and Data Buses x
2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port
2.3.8. RISC-V based Debug Module x
2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Trigger 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/g Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Multipy and Divide Units 3.3.4. Custom Instruction 3.3.5. Reset and Debug Signals 3.3.6. Control and Status Registers 3.3.7. Exception Controller 3.3.8. Interrupt Controller 3.3.9. Memory and I/O Organization 3.3.10. RISC-V based Debug Module
3.3.8. Interrupt Controller x
3.3.8.1. Timer and Software Interrupt Module
3.3.9. Memory and I/O Organization x
3.3.9.1. Instruction and Data Buses 3.3.9.2. Address Map 3.3.9.3. Cache Memory
3.3.9.1. Instruction and Data Buses x
3.3.9.1.1. Instruction Manager Port 3.3.9.1.2. Data Manager Port
3.3.9.3. Cache Memory x
3.3.9.3.1. Instruction Cache 3.3.9.3.2. Data Cache 3.3.9.3.3. Configurable Cache Memory 3.3.9.3.4. Bypassing Cache (Peripheral Region) 3.3.9.3.5. Using Cache Memory Effectively
3.3.10. RISC-V based Debug Module x
3.3.10.1. Debug Mode 3.3.10.2. Halt from Debug Module 3.3.10.3. Trigger 3.3.10.4. Abstract Commands in Debug Mode 3.3.10.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
1. Overview
2. Nios® V/m Processor
3. Nios® V/g Processor
4. Nios V Processor Reference Manual Archives
5. Document Revision History for the Nios® V Processor Reference Manual

3.3.9.3.2. Data Cache

The data cache memory has the following characteristics:

  • Direct-mapped cache implementation
  • 32 bytes (8 words) per cache line
  • Configurable size of 1, 2, 4, 8, and 16 KBytes
  • The data manager port reads an entire cache line at a time from memory, and issues one read per clock cycle.
  • Write-back
  • Write-allocate (i.e., on a store instruction, a cache miss allocates the line for that address)

The data byte address size is 32 bit. The size of the tag and index field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-byte line).

The Nios® V/g processor instruction set provides cache block management instructions for the data cache.

Table 52.  RISC-V Zicbom Cache Block Management
Instruction Name Operation Encoding
cbo.clean <rs1> 1 2 Clean Data Cache Address
  • Identifies the cache line with tag and index field.
  • If there is a cache hit, proceeds to the following operations:
    • Clears the cache line’s dirty state.
    • Keeps the cache line’s valid state.
    • If the cache line is valid and dirty, data is written back to the memory.
 Refer to RISC-V Base Cache Management Operation ISA Extension.
cbo.flush <rs1> 1 2 Flush Data Cache Address
  • Identifies the cache line with tag and index field.
  • If there is a cache hit, proceeds to the following operations:
    • Invalidates the cache line.
    • Writes the data back to the memory if the cache line is valid and dirty; otherwise, ignores the data.
cbo.inval <rs1> 1 2 Invalidate Data Cache Address
  • Identifies the cache line with tag and index field.
  • If there is a cache hit, proceeds to the following operations:
    • Invalidates the cache line.
    • Does not write the data back to the memory.
Table 53.  Custom Cache Block Management Instructions
Instruction Operation Encoding
cbo.clean.ix <rs1>[ 3
  • Identifies the cache line with index field,
  • Clears the cache line’s dirty state.
  • Keeps the cache line’s valid state.
  • If the cache line is valid and dirty, data is written back to the memory.
 Refer to Encoding for cbo.clean.ix
cbo.flush.ix <rs1> 3
  • Identifies the cache line with index
  • Invalidates the cache line.
  • If the cache line is valid and dirty, data is written back to the memory.
  • If the cache line is not dirty, data is not written back to the memory field,
 Refer to Encoding for cbo.flush.ix
cbo.inval.ix <rs1>[ 3
  • Identifies the cache line with index field,
  • Invalidates the cache line.
  • Data is not written back to the memory.
 Refer to Encoding for cbo.inval.ix
Table 54.  Encoding for cbo.clean.ix
Bit Field
31:20 19:15 14:12 11:7 6:0
imm rs1 cbo Reserved misc-mem
000010000001 rs1 010 00000 0001111
Table 55.  Encoding for cbo.flush.ix
Bit Field
31:20 19:15 14:12 11:7 6:0
imm rs1 cbo Reserved misc-mem
000010000010 rs1 010 00000 0001111
Table 56.  Encoding for cbo.inval.ix
Bit Field
31:20 19:15 14:12 11:7 6:0
imm rs1 cbo Reserved misc-mem
000010000000 rs1 010 00000 0001111
1 Source register 1 (rs1) holds the 32-bit cache line address (tag, index, and offset).
2 If the specified cache line address is not found (cache miss), these instruction are implemented as nop, and does no changes to any cache lines.
3 Source register 1 (rs1) holds the cache line index, which can be 5 to 9-bits depending on the cache size.
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