Nios® V Processor Reference Manual

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ID 683632
Date 5/26/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/m Processor 3. Nios® V/g Processor 4. Nios V Processor Reference Manual Archives 5. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module
2.3.6. Interrupt Controller x
2.3.6.1. Timer and Software Interrupt Module
2.3.7. Memory and I/O Organization x
2.3.7.1. Instruction and Data Buses 2.3.7.2. Address Map
2.3.7.1. Instruction and Data Buses x
2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port
2.3.8. RISC-V based Debug Module x
2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Trigger 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/g Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Multipy and Divide Units 3.3.4. Custom Instruction 3.3.5. Reset and Debug Signals 3.3.6. Control and Status Registers 3.3.7. Exception Controller 3.3.8. Interrupt Controller 3.3.9. Memory and I/O Organization 3.3.10. RISC-V based Debug Module
3.3.8. Interrupt Controller x
3.3.8.1. Timer and Software Interrupt Module
3.3.9. Memory and I/O Organization x
3.3.9.1. Instruction and Data Buses 3.3.9.2. Address Map 3.3.9.3. Cache Memory
3.3.9.1. Instruction and Data Buses x
3.3.9.1.1. Instruction Manager Port 3.3.9.1.2. Data Manager Port
3.3.9.3. Cache Memory x
3.3.9.3.1. Instruction Cache 3.3.9.3.2. Data Cache 3.3.9.3.3. Configurable Cache Memory 3.3.9.3.4. Bypassing Cache (Peripheral Region) 3.3.9.3.5. Using Cache Memory Effectively
3.3.10. RISC-V based Debug Module x
3.3.10.1. Debug Mode 3.3.10.2. Halt from Debug Module 3.3.10.3. Trigger 3.3.10.4. Abstract Commands in Debug Mode 3.3.10.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
1. Overview
2. Nios® V/m Processor
3. Nios® V/g Processor
4. Nios V Processor Reference Manual Archives
5. Document Revision History for the Nios® V Processor Reference Manual

2.3.8.2. Halt from Debug Module

Debugger can write to the haltreq bit in Debug Module Control (dmcontrol) register, which places the Nios® V processor in debug mode after some handshake. The assertion of haltreq bit sends an asynchronous interrupt to the processor core logic.

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