Nios® V Processor Reference Manual

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ID 683632
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Control and Status Registers 2.3.4. Exception Controller 2.3.5. Interrupt Controller 2.3.6. Memory and I/O Organization 2.3.7. RISC-V based Debug Module
2.3.5. Interrupt Controller x
2.3.5.1. Timer and Software Interrupt Module
2.3.6. Memory and I/O Organization x
2.3.6.1. Instruction and Data Buses
2.3.6.1. Instruction and Data Buses x
2.3.6.1.1. Instruction Manager Port 2.3.6.1.2. Data Manager Port 2.3.6.1.3. Address Map
2.3.7. RISC-V based Debug Module x
2.3.7.1. Debug Mode 2.3.7.2. Halt from Debug Module 2.3.7.3. Debug Implementation 2.3.7.4. Abstract Commands in Debug Mode 2.3.7.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Document Revision History for the Nios® V Processor Reference Manual

2.2. Processor Pipeline

The Nios V/m processor employs a 5-stages pipeline.

Table 4.  Processor Pipeline Stages
Stage Denotation Function
Instruction Fetch F
  • PC+4 calculation
  • Next instruction fetch
  • Pre-decode for register file read
Instruction Decode D
  • Decode the instruction
  • Register file read data available
  • Hazard resolution and data forwarding
Instruction Execute E
  • ALU operations
  • Memory address calculation
  • Branch resolution
  • CSR read/write
Memory M
  • Memory and multicycle operations
  • Register file write
  • Branch redirection
Write Back W
  • Facilitates data dependency resolution by providing General Purpose Register value.

The Nios® V/m processor implements the General Purpose Register file using M20K memory block. It takes one cycle to read from a M20K location. Hence, the F-stage initiates register file reads so General Purpose Register values are available in D-stage.

It takes two cycles to write to a M20K location. Hence, the M-stage initiates writes to a General Purpose Register and carries forward the value to W-stage, if there is a dependency to be resolved.

The core resolves data dependencies in D-stage, and operands can move from register file read or E-stage, M-stage, or W-stage.

The pipeline can stall due to following reasons:
  • Data dependency: If the source operand is not available in D-stage, instruction in D-stage and F-stage stalls until the operand becomes available. The scenario can happen if destination General Purpose Register of load or multicycle instruction in E-stage or M-stage is the source for instruction in D-stage.
  • Resource stall: If a memory operation or multicycle is pending in M-stage, the instructions in preceding stages stalls until M-stage completes the instruction.
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