Nios® V Processor Reference Manual

Download PDF
ID 683632
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Control and Status Registers 2.3.4. Exception Controller 2.3.5. Interrupt Controller 2.3.6. Memory and I/O Organization 2.3.7. RISC-V based Debug Module
2.3.5. Interrupt Controller x
2.3.5.1. Timer and Software Interrupt Module
2.3.6. Memory and I/O Organization x
2.3.6.1. Instruction and Data Buses
2.3.6.1. Instruction and Data Buses x
2.3.6.1.1. Instruction Manager Port 2.3.6.1.2. Data Manager Port 2.3.6.1.3. Address Map
2.3.7. RISC-V based Debug Module x
2.3.7.1. Debug Mode 2.3.7.2. Halt from Debug Module 2.3.7.3. Debug Implementation 2.3.7.4. Abstract Commands in Debug Mode 2.3.7.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Document Revision History for the Nios® V Processor Reference Manual

2.1. Processor Performance Benchmarks

Table 1.  fmax (MHz)
Device Family Nios® V/m Processor
Intel® Cyclone® 10 270.27
Intel® Arria® 10 305.62
Intel® Stratix® 10 361.93
Intel® Agilex™ 566.25
Table 2.  Logic Size
Device Family Nios® V/m Processor
Intel® Cyclone® 10 1375
Intel® Arria® 10 1375
Intel® Stratix® 10 1580
Intel® Agilex™ 1509
Table 3.  Architecture Performance
Performance Metric Nios® V/m Processor
DMIPS/MHz Ratio 0.464
CoreMark/MHz Ratio 0.32148
Intel uses the following options for this benchmark:
  • Maximum performance result based on 10 Seed Sweep from Intel® Quartus® Prime Design Suite software version 21.3.
  • Fastest speed grade from each device family.
  • Peripherals:
    • Nios® V/m processor core
    • 4KB On-Chip Memory for Instruction Bus
    • 4KB On-Chip Memory for Data Bus
    • Avalon® Memory-Mapped Pipeline Bridge
  • Intel® Quartus® Prime software compiler settings. Intel uses the same Intel® Quartus® Prime design example for FMAX and Logic Size benchmark but with different compiler setup:
    • FMAX: superior_performance_optimized_placement_effort
    • Logic Size: area_aggressive
  • Toolchain:
    • Version Number:
      • xPack GNU RISC-V Embedded GCC, Linux 64-bit version: 10.1.1.0-1.1
      • CMake Version: 3.14.2
    • Compiler Configurations:
      • Compiler flags: -03
      • Assembler options: -Wa -gdwarf2
      • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Disclaimer: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.
Level Two Title