Nios® V Processor Reference Manual

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ID 683632
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Control and Status Registers 2.3.4. Exception Controller 2.3.5. Interrupt Controller 2.3.6. Memory and I/O Organization 2.3.7. RISC-V based Debug Module
2.3.5. Interrupt Controller x
2.3.5.1. Timer and Software Interrupt Module
2.3.6. Memory and I/O Organization x
2.3.6.1. Instruction and Data Buses
2.3.6.1. Instruction and Data Buses x
2.3.6.1.1. Instruction Manager Port 2.3.6.1.2. Data Manager Port 2.3.6.1.3. Address Map
2.3.7. RISC-V based Debug Module x
2.3.7.1. Debug Mode 2.3.7.2. Halt from Debug Module 2.3.7.3. Debug Implementation 2.3.7.4. Abstract Commands in Debug Mode 2.3.7.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Document Revision History for the Nios® V Processor Reference Manual

2.3.6.1.2. Data Manager Port

The Nios® V/m processor data bus is implemented as a 32-bit AMBA* 4 AXI manager port. The data manager port performs two functions:

  • Read data from memory or a peripheral when the processor executes a load instruction.
  • Write data to memory or a peripheral when the processor executes a store instruction.

axsize signal value indicates the load/store instruction size- byte (LB/SB), halfword (LH/SH) or word (LW/SW). Address on axaddr signal is always aligned to size of the transfer. For store instructions, respective writes strobe bits are asserted to indicate bytes being written.

Nios® V/m processor core does not support speculative issue of load/store instruction. Hence, a core can issue only one load or store instruction and waits until the issued instruction is complete.

Table 9.  Data Interface Signals
Interface Signal Role Direction
Write Address Channel awaddr Store address Output
awprot Undefined- constant value Output
awvalid Store valid Output
awsize Store size- SB, SH, SW Output
awready From memory/interconnect Input
Write Data Channel wvalid Store valid Output
wdata Store data Output
wstrb Byte position in word Output
wlast Constant 1 Output
wready From memory/interconnect Input
Write Response Channel bvalid Store done Input
bresp [1:0] Store done status: Non-zero value denotes store access fault exception. Input
bready Constant 1 Output
Read Address Channel araddr Load Address Output
arprot Undefined- constant value Output
arvalid Load Valid Output
arsize Load size: LB, LH, LW Output
arready From subordinate/interconnect Input
Read Data Channel rdata Read data Input
rvalid Read data valid Input
rresp Load response status: Non-zero value denotes load access fault exception. Input
rready Constant 1 Output
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