1.6. Test Result Comments
In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRBS and Ramp checker.
In deterministic measurement test case DL.3, the link clock count in the FPGA depends on the board layout and the LMFC offset value set in the ADC register. The link clock count can vary by only one link clock when the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic latency measurement is caused by word alignment, where the control characters fall into the next cycle of data sometime after realignment. This makes the duration of ILAS phase longer by one link clock sometimes after reset or power cycle.
For modes with 8 converters (M=8), the result is updated with ‘PASS with comments’ because the test cases TL.1, TL.2 and DL.4 are validated only for first 7 converters due to known limitation of ADC. The ADC does not output RAMP/PRBS test-pattern for the 8th converter and this is documented in the ADC’s datasheet in TEST MODES section on page 54.
For a few modes, in order to avoid lane de-skew error or achieve deterministic latency, RBD offset and LMFC offset registers had to be programmed. The modes and the corresponding values used are tabled below.
| Mode (LMF) | csr_lmfc_offset | csr_rbd_offset |
|---|---|---|
| 211-K20 |
2 |
0 |
| 421-K20 |
0 |
2 |
| 821-K20 |
0 |
1 |
| 411-K20 |
2 |
0 |
| 841-K20 |
0 |
2 |