AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report

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ID 683626
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report
1. Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 779: Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report

1.7. Document Revision History for AN 779: Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report

Date Version Changes
December 2017 2017.12.18
  • Renamed the document as AN 779: Intel FPGA JESD204B IP Core and AD9691 Hardware Checkout Report.
  • Added a note to clarify that the IOPLL input reference clock is sourcing from device clock through global clock network in the Hardware Setup topic.
  • Updated for latest branding standards.
May 2017 2017.05.08 Rebranded as Intel.
October 2016 2016.10.31 Initial release.
Level Two Title