AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report

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ID 683626
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report
1. Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 779: Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report

1.4. JESD204B IP Core and ADC Configurations

The JESD204B IP Core parameters (L, M and F) in this hardware checkout are natively supported by the AD9691 device's quick configuration register at address 0x570. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9691 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Table 6.  Parameter ConfigurationGlobal settings for all configuration:
  • N = 14
  • N' = 16
  • CS = 0
  • CF = 0
  • FPGA Device Clock = 312.5 MHz (The device clock is used to clock the transceiver.)
  • FPGA Management Clock = 100 MHz
  • Character Replacement = Enabled
  • Data Pattern = PRBS-9, Ramp1
LMF HD S ADC Sampling Clock (MHz) FPGA Frame Clock (MHz) 2 FPGA Link Clock (MHz)2 Lane Rate (Gbps) DDC enabled
112 0 1 625 312.5 312.5 12.5 No
211 1 1 1250 312.5 312.5 12.5 No
212 0 2 1250 312.5 312.5 12.5 No
411 1 2 1250 156.25 156.25 6.25 No
412 0 4 1250 156.25 156.25 6.25 No
811 1 4 1250 78.125 78.125 3.125 No
812 0 8 1250 78.125 78.125 3.125 No
124 0 1 312.5 312.5 312.5 12.5 No
222 0 1 625 312.5 312.5 12.5 No
421 1 1 1250 312.5 312.5 12.5 No
422 0 2 1250 312.5 312.5 12.5 No
821 1 2 1250 156.25 156.25 6.25 No
822 0 4 1250 156.25 156.25 6.25 No
148 0 1 312.5 156.25 312.5 12.5 Yes
244 0 1 625 312.5 312.5 12.5 Yes
442 0 1 1250 312.5 312.5 12.5 Yes
841 1 1 1250 156.25 156.25 6.25 Yes
842 0 2 1250 156.25 156.25 6.25 Yes
288 0 1 312.5 156.25 312.5 12.5 Yes
484 0 1 625 312.5 312.5 12.5 Yes
882 0 1 1250 312.5 312.5 12.5 Yes
1 Ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, DL.3 and DL.4 only.
2 The frame clock and link clock is derived from the device clock using an internal PLL.
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