AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

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ID 683624
Date 1/29/2020
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Document Table of Contents
Document Table of Contents x
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission x
1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1.1. PCB Material Selection x
1.1.1. Loss Tangent and Dissipation Factor 1.1.2. Dielectric Constant 1.1.3. Fiberglass Weave 1.1.4. Copper Surface Roughness
1.3. Channel Design x
1.3.1. BGA Channel Breakout 1.3.2. Channel Routing Design 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization
1.3.2. Channel Routing Design x
1.3.2.1. Trace Width Selection 1.3.2.2. Loose vs. Tight Coupled Traces 1.3.2.3. Crosstalk Control
1.4. Summary x
1.4.1. PCB Material Selection 1.4.2. Stackup Design 1.4.3. Channel Design 1.4.4. References
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

1.3.1. BGA Channel Breakout

As the number of very high-speed transceiver pairs on FPGAs continue to increase, the complexity of the channel breakout design increases as well. Trace breakout can typically use either a single trace or dual trace topology between the BGA via grid.

Figure 13. Single Trace BreakoutRouting layers are separated by a GND plane.

Single Trace Breakout

Figure 14. Dual Trace BreakoutRouting layers are separated by a GND plane.

Dual Trace Breakout

In the single trace breakout, more layers are required to fully route all the TX and RX transceiver pairs because only one trace is routed between the BGA via grid per layer. Because there is ample space for a maximum trace width of up to 13.37 mils (assuming typical minimum trace-to-copper clearances of 4 mils for the recommended 18 mil via pad size and 39.37 mil via-to-via center pitch), the trace width and resulting characteristic impedance is easily made uniform throughout the trace route.

In the dual trace breakout, two traces are used to reduce layer count requirement, but their maximum trace width is limited to 4.68 mils because of the same trace-to-copper clearance requirements. Because high-speed transceiver traces are usually routed using trace widths of 6 to 8 mils (or more) to reduce the impact of skin effect losses at higher frequencies, the reduction of trace width to accommodate dual trace breakout effectively increases the trace impedance. However, this increase is offset by the reduction of the trace-to-trace separation in the differential pair, so the net impedance remains unchanged.

Table 3.  Net Impedance Effect of Trace Neck Down
Topology Height from Reference Plane (H1/H2 in mils) Er Trace Width (W in mils) Trace Separation (S in mils) Diff Zo (Ω)
Stripline 9/9 3.7 6 6.5 100
Stripline 9/9 3.7 4 4 101

Another benefit of the trace neck down is that the thinner trace width increases the trace inductance and helps to compensate for the higher capacitance of the BGA ball pad.

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