As transceiver data rates increase and the unit interval time (UI) decrease, the end-to-end link design of a transceiver channel becomes increasingly critical to the overall performance of the link. Consider a Stratix® V FPGA with transceiver channels operating up to 28 Gbps. At this data rate, the UI is less than 36 ps. Any signal degradation of the channel can impact jitter margin and increase eye closure, resulting in increased bit error rates (BER). Two of the proposed standards for 100-Gpbs data transmission using fewer lanes are CEI-25G-LR and CEI-28G-VSR.
CEI-25G-LR is intended for 25 Gbps data transmission across long-reach backplane architectures. Likewise, CEI-28G-VSR specifies a 28-Gbps data rate for very short-reach chip-to-module and chip-to-chip applications. For these standards, the total insertion loss budget for the link at the Nyquist rate is approximately -25 dB for CEI-25G-LR and -10 dB for CEI-28G-VSR. Successful data transmission across these types of links requires the designer to minimize signal degradation caused by the channel to meet stringent loss requirements. Understanding the various factors that contribute to channel loss allows the designer to make appropriate design choices to mitigate adverse effects and achieve optimal link performance. This application note describes how to optimize a complete transceiver link for these very high-Gbps data transmission designs.
A typical end-to-end transceiver link can be separated into three main components:
Designers must give careful consideration to each of these components to avoid degraded link performance. Link optimization involves understanding and managing the first-order factors that impact signal performance for each of the three components. For high-speed signal transmission, these first-order factors are: