F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3. Parameter Settings

You customize the F-Tile Interlaken Intel® FPGA IP core using the IP parameter editor.
Table 12.  Main: General
Parameter Supported Values Default Setting Description
PMA Type FGT

FHT

FGT
Specifies the type of transceiver for your design.
  • FGT is a 53.125G transceiver
  • FHT is a 106.25G transceiver
Note: This parameter is only available when the Transceiver mode is PAM4.
Meta fame length 128-8192 2048

Specifies the meta frame length in 64-bit (8-byte) words. Must be a power of two.

Smaller values shorten the time to achieve lock. Larger values reduce the overhead while transferring data, after the clock data recover (CDR) circuit achieves lock.

Number of lanes 4

6

8

10

12

16

20

24

8 This parameter specifies the number of lanes available for Interlaken communication.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to Table: IP Supported Combinations of Number of Lanes and Data Rate in this document.

Data rate (Gbps) 6.25

10.3125

12.5

25.78125

26.5625

28.125

12.5 Gbps This parameter specifies the data rate on each lane.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to Table: IP Supported Combinations of Number of Lanes and Data Rate in this document.

Transceiver reference clock frequency Multiple

For FHT transceiver type: 156.25 MHz

For FGT transceiver type: Multiple, depending on the selected transceiver data rate.

This parameter specifies the expected frequency of the pll_ref_clk input clock.

If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.

Enable Interlaken Look-aside mode On

Off

Off Enable this option to configure the IP core in Interlaken Look-aside mode.
Enable M20K ECC support On

Off

Off This parameter specifies whether your Interlaken IP variation supports the ECC feature in the M20K memory blocks that are configured as part of the IP.

You can turn this parameter on to enable single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP. This feature enhances data reliability but increases latency and resource utilization.

Include 32bit soft CWBIN counters

On

Off

Off

This parameter is available for PAM4 mode only. This soft logic converts the 8-bit CWBin0-3 registers in Hard IP (FEC block of F-tile) to the 32-bit registers in Soft logic.

Reconfig clock frequency

100 MHz to 250 MHz

100 MHz

Provides the clock frequency of the reconfig_ilk_clk port to allow the IP to estimate the timeout for CWBIN counter.

The clock supports 100 MHz to 250 MHz frequency. This frequency must be same as the frequency driven to mm_clk.

This feature is supported for PAM4 mode with 32bit soft CWBIN counters enabled.

Enable EFIFO support On

Off

Off Enable this parameter when the SystemPLL clock frequency is not same as the PMA clock frequency.
Note: You must enable EFIFO for FHT PMAs due to existence of PPM between FHT and F-tile SystemPLL when the refclk source is not shared.
System PLL clock frequency User defined 830.078125 MHz Set the desired SystemPLL clock frequency when the SystemPLL clock frequency is not same as the PMA clock frequency. The SystemPLL clock frequency must be higher than transceiver clock frequency.
Note: This parameter is only available when the Enable EFIFO support is turned on. This feature is only supported for PAM4 mode.
This value must match the SystemPLL clock which is connected to the IP core.
System PLL reference clock frequency Multiple 156.25 MHz Set the desired SystemPLL reference clock frequency when the SystemPLL clock frequency is not same as the PMA clock frequency.
Note: This parameter is only available for design example generation when the Enable EFIFO support is turned on.
Enable debug endpoint for Datapath and PMA Avalon® memory-mapped interface

On

Off

Off When turned On, the F-Tile Interlaken Intel® FPGA IP core includes an embedded Debug Endpoint that internally connects the Avalon memory-mapped agent interface. The Debug Endpoint can access the reconfiguration space of the PMA interface block. it can perform certain tests and debug functions through JTAG using the System Console. This option may require that you include a jtag_debug link in the system.
Table 13.  In-Band Flow Control
Parameter Supported Values Default Setting Description
Include in-band flow control functionality On

Off

Off This parameter specifies whether your Interlaken IP includes an in-band flow control block.
Number of calendar pages 1

2

4

8

16

1 This parameter specifies the number of 16-bit pages of in-band flow control data that your Interlaken IP supports. This parameter is available if you turn on Include in-band flow control functionality.

Each 16-bit calendar page includes 16 in-band flow control bits. The application determines the interpretation of the in-band flow control bits. The IP supports a maximum of 256 channels with in-band flow control.

If your design requires a different number of pages, select the lowest supported number of pages which is larger than the number required, and ignore any unused pages. For example, if your configuration requires three in-band flow control calendar pages, you can set this parameter to 4 and use pages 3, 2, and 1 while ignoring page 0.
Table 14.  Transceiver Settings
Transceiver Settings Parameter Supported Values Default Setting Description
TX scrambler seed 0x3ab1278890105cd

This parameter specifies the initial scrambler state. If you configure a single Interlaken IP on your device, you can use the default value of this parameter.

If you configure multiple Interlaken IPs, you must use a different initial scrambler state for each IP. Select random values for each Interlaken IP. Each scrambler seed should have an approximately even mix of ones and zeros. The scrambler seeds should differ from the other scramblers in multiple spread out bit positions.

Transceiver mode NRZ

PAM4

NRZ Specifies the transceiver modulation mode.
Table 15.  User Data Transfer Interface
Parameter Supported Values Default Setting Description
Transfer mode selection Packet

Interleaved

Packet Supports two modes for packet transfer flexibility and ASIC/ASSP/FPGA/SoC interoperability.
Number of Segments 1

2

4

1 This parameter enables 1, 2, or 4 segments depending on the total number of words.