F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Analog Parameter Settings 2.5. Reference and System PLL Clock for your IP Design 2.6. Simulating the IP Core 2.7. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Reference and System PLL Clock for your IP Design x
2.5.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

1.4. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved Mode (number of segments = 1)The following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 23.1
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18465.7 40,918 7,661 28
10.3125 12 58119.5 112,695 18,757 73
12.5 4 18426.5 41,033 7,680 28
8 37706.9 76,389 13,598 52
10 47734.4 93,991 16,426 61
12 58129.1 112,545 18,837 73
25.78125 4 18643.3 41,728 7,882 28
6 29491.0 63,601 11,641 52
8 37957.4 77,118 14,284 52
10 52877.2 109,813 18,612 100
12 62864.4 126,254 21,962 100
PAM4 FGT 53.125 2 18137.2 45,216 8,766 28
2 (efifo) 18481.3 45,571 8,707 28
4 36650.4 83,968 15,862 52
4 (efifo) 37483.6 84,619 15,907 52
6 60330.9 136,261 24,195 100
6 (efifo) 61459.9 137,953 23,701 100
8 80513.8 178,009 30,546 100
8 (efifo) 82241.6 176,034 29,942 100
10 105536.1 229,156 37,323 121
10 (efifo) 107661.1 228,985 37,218 121
12

141257.7

 303,436 46,445 196

12 (efifo)

143633.2

308,624

46,898

196
56.25 10 106278.0 228,999 37,656 121
10 (efifo) 107341.3 230,514 38,084 121
12 142230.6 306,052 46,767 196
12 (efifo) 143426.3 308,382 47,119 196
FHT 106.25 1 (efifo) 18434.6 45,641 8,664 28
2 (efifo) 37464.4 84,366 16,107 52
3 (efifo) 61529.1 137,593 23,934 100
4 (efifo) 82031.6 178,554 31,282 100
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 23.1
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18403.2 41,207 7,486 28
10.3125 12 58161.9 112,615 18,824 73
12.5 4 18425.2 40,999 7,655 28
8 37687.6 76,141 13,622 52
10 47674.3 94,177 16,211 61
12 58135.5 112,667 18,680 73
25.78125 4 18612.1 41,550 8,028 28
6 29462.7 63,520 11,710 52
8 37957.8 77,045 14,366 52
10 52848.1 109,563 18,902 100
12 62814.1 126,599 21,647 100
PAM4 FGT 53.125 2 18143.3 45,276 8,712 28
2 (efifo) 18528.3 45,665 8,642 28
4 36708.5 83,876 15,889 52
4 (efifo) 37523.8 84,688 15,708 52
6 60259.9 136,678 23,764 100
6 (efifo) 61479.4 137,597 23,808 100
8 80500.7 176,969 31,462 100
8 (efifo) 81938.2 179,018 30,894 100
10 105421.5 228,426 37,985 121
10 (efifo) 107570.6 230,243 37,981 121
12 141144.5 305,678 47,747 196
12 (efifo) 143398.5 308,425 47,059 196
56.25 10 106226.5 229,018 37,768 121
10 (efifo) 107276.0 230,310 38,337 121
12 142238.9 306,375 47,018 196
12 (efifo) 143356.6 308,161 47,279 196
FHT 106.25 1 (efifo) 18476.2 45,553 8,683 28
2 (efifo) 37465.5 84,686 15,815 52
3 (efifo) 61442.1 137,556 23,956 100
4 (efifo) 81984.2 178,901 30,841 100
Table 6.  Resource Utilization for Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 23.1
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 13707.7 31105 5616 0
10.3125 12 43822.5 82094 15607 0
12.5 4 13723.2 31056 5594 0
8 27951.3 55493 10464 0
10 35759.9 70421 12538 0
12 43819.1 82306 15490 0
25.78125 4 13706.6 31083 5895 0
6 20676.1 43430 8418 0
8 27968.0 55664 10691 0
10 35814.8 70339 13442 0
12 43835.9 82678 15809 0
PAM4 FGT 53.125 2 13219.4 34925 6571 0
2 (efifo) 13635.5 35445 6409 0
4 26950.8 63028 12070 0
4 (efifo) 27680.3 63614 12325 0
6 42280.9 93009 18314 0
6 (efifo) 43194.3 94078 18216 0
FHT 53.125 1 (efifo) 13581.9 35313 6518 0
2 (efifo) 27713.1 63406 12450 0
3 (efifo) 43129.8 94250 17951 0
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