F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 10/02/2023
Public

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Document Table of Contents

1.1. Features

The F-Tile Interlaken Intel® FPGA IP core supports the following features:
  • General features:
    • Compliant with the Interlaken Protocol Specification, Revision 1.2.
    • Compliant with the Interlaken Reed-Solomon Forward Error Correction (RS-FEC) Extension Specification, Revision 1.1.
    • Supports 1, 2, 3, 4, 6, 8, 10, and 12 serial lanes in configurations that provide up to 675 Gbps raw bandwidth. Refer to the Table: IP Supported Combinations of Number of Lanes and Data Rates below for more details on current list of supported configurations.
    • Supports per-lane data rates of 6.25, 10.3125, 12.5, 25.78125, 53.125, 56.25, and 106.25 Gbps using the Intel FPGA on-chip high-speed transceivers.
    • All variants support the Interlaken Look-aside Mode.
  • User interface features:
    • Supports dynamically configurable BurstMax and BurstMin values.
    • Supports Packet mode and Interleaved mode for user data transfer.
    • Supports up to 256 logical channels in out-of-the-box configuration.
    • Supports multi-segment user interface.
  • Flow-control features:
    • Supports optional out-of-band flow control blocks.
    • Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
    • Supports error correction code (ECC) for memory block implementation with the IP.
  • Line-side features:
    • Supports per-lane data rate of 53.125 and 56.25 Gbps using pulse amplitude modulation (PAM4) FGT PMAs and 106.25 Gbps using the PAM4 FHT PMAs.
    • Supports per lane data rates of 6.25, 10.3125, 12.5, 25.78125 Gbps using non-return-to-zero (NRZ) mode.
Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the Intel® Quartus® Prime Pro Edition software version 23.1.
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5 25.78125 53.125 56.25 106.25
1 - - - - - - Yes
2 - - - - Yes - Yes
3 - - - - - - Yes
4 Yes - Yes Yes Yes - Yes
6 - - - Yes Yes - -
8 - - Yes Yes Yes - -
101 - - Yes Yes Yes Yes -
12 - Yes Yes Yes Yes Yes -
Table 2.  IP Theoretical Raw Aggregate BandwidthThe following combinations are supported in the Intel® Quartus® Prime Pro Edition software version 23.1
PMA Type Lane Rate (Gbps) Number of Lanes User Interface Width (words) Data Width (bits) Raw Aggregate Bandwidth (Gbps)
FGT 6.25 4 4 256 25
10.3125 12 8 512 123.75
12.5 4 4 256 50
8 8 512 100
10 8 512 125
12 8 512 150
25.78125 4 4 256 103.125
6 8 512 154.6875
8 8 512 206.25
10 16 1024 257.8125
12 16 1024 309.375
53.125 2 4 256 106.25
4 8 512 212.5
6 16 1024 318.75
8 16 1024 425
10 16 1024 531.25
12 32 2048 637.5
56.25 10 16 1024 562.5
12 32 2048 675
FHT 106.25 1 4 256 106.25
2 8 512 212.5
3 16 1024 318.75
4 16 1024 425
1 For a 10-lane configuration design, the F-tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew.