Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Public
Document Table of Contents

8.5.89. stw / stwio

Instruction store word to memory or I/O peripheral
Operation

Mem32[rA + σ(IMM16)] ←  rB

Assembler Syntax

stw rB, byte_offset(rA)

stwio rB, byte_offset(rA)

Example

stw r6, 100(r5)

Description

Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. Stores rB to the memory location specified by the effective byte address. The effective byte address must be word aligned. If the byte address is not a multiple of 4, the operation is undefined.

Usage

In processors with a data cache, this instruction may not generate an Avalon® -MM data transfer immediately. Use the stwio instruction for peripheral I/O. In processors with a data cache, stwio bypasses the cache and is guaranteed to generate an Avalon® -MM bus cycle. In processors without a data cache, stwio acts like stw.

Exceptions

Supervisor-only data address

Misaligned data address

TLB permission violation (write)

Fast TLB miss (data)

Double TLB miss (data)

MPU region violation (data)

Instruction Type

I

Instruction Fields

A = Register index of operand rA

B = Register index of operand rB

IMM16 = 16-bit signed immediate value

Table 119.  stw
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x15
Table 120.  stwio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x35