Visible to Intel only — GUID: nik1398707032259
Ixiasoft
Visible to Intel only — GUID: nik1398707032259
Ixiasoft
3.1.3.2. fPLL IP Core
Parameters | Range | Description |
---|---|---|
fPLL Mode |
Core Cascade Source Transceiver |
Specifies the fPLL mode of operation. Select Core to use fPLL as a general purpose PLL to drive the FPGA core clock network. Select Cascade Source to connect an fPLL to another PLL as a cascading source. Select Transceiver to use an fPLL as a transmit PLL for the transceiver block. |
Protocol Mode |
Basic PCIe* Gen1 PCIe Gen2 SDI_direct SATA TX |
Governs the internal setting rules for the VCO. This parameter is not a preset. You must set all parameters for your protocol. |
Enable fractional mode |
On/Off |
Enables the fractional frequency mode. This enables the PLL to output frequencies which are not integral multiples of the input reference clock. |
Enable manual counter configuration |
On/Off |
Selecting this option allows you to manually specify M, N, C and L counter values. |
Enable clklow and fref ports 55 |
On/Off |
Enables fref and clklow clock ports for external lock detector. In Transceiver mode when "enable fractional mode" and "SDI_direct" prot_mode are selected, pll_locked port is not available and user can create external lock detector using fref and clklow clock ports. |
Desired Reference clock frequency |
Refer to the GUI |
Specifies the desired PLL input reference clock frequency. |
Actual reference clock frequency |
Read-only |
Displays the actual PLL input reference clock frequency. |
Number of PLL reference clocks |
1 to 5 |
Specify the number of input reference clocks for the fPLL. |
Selected reference clock source |
0 to 4 |
Specifies the initially selected reference clock input to the fPLL. |
Bandwidth |
Low Medium High |
Specifies the VCO bandwidth. Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection. |
Operation mode |
Direct Feedback compensation bonding |
Specifies the feedback operation mode for the fPLL. |
Multiply factor (M-counter) |
8 to 127 (integer mode) 11 to 123 (fractional mode) |
Specifies the multiply factor (M-counter). |
Divide factor (N-counter) |
1 to 31 |
Specifies the divide factor (N-counter). |
Divide factor (L-counter) |
1, 2, 4, 8 |
Specifies the divide factor (L-counter). |
Divide factor (K-counter) |
User defined |
Specifies the divide factor (K-counter). |
PLL output frequency |
Read-only |
Displays the target output frequency for the PLL. |
PLL Datarate |
Read-only |
Displays the PLL datarate. |
Parameters | Range | Description |
---|---|---|
Include Master Clock Generation Block |
On/Off |
When enabled, includes a master CGB as a part of the fPLL IP core. The PLL output drives the master CGB. This is used for x6/xN bonded and non-bonded modes. |
Clock division factor |
1, 2, 4, 8 |
Divides the master CGB clock input before generating bonding clocks. |
Enable x6/xN non-bonded high-speed clock output port |
On/Off |
Enables the master CGB serial clock output port used for x6/xN non-bonded modes. |
Enable PCIe clock switch interface |
On/Off |
Enables the control signals used for PCIe clock switch circuitry. |
MCGB input clock frequency |
Read only |
Displays the master CGB’s required input clock frequency. You cannot set this parameter. |
MCGB output data rate |
Read only |
Displays the master CGB’s output data rate. You cannot set this parameter. This value is calculated based on MCGB input clock frequency and MCGB clock division factor. |
Enable bonding clock output ports |
On/Off |
Enables the tx_bonding_clocks output ports of the Master CGB used for channel bonding. You must enable this parameter for bonded designs. |
Enable feedback compensation bonding |
On/Off |
Enables the feedback output path of the master CGB used for feedback compensation bonding. When enabled, the feedback connections are automatically handled by the PLL IP. |
PMA interface width |
8, 10, 16, 20, 32, 40, 64 |
Specifies the PMA-PCS interface width. Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core. |
Parameter | Range | Description |
---|---|---|
Enable dynamic reconfiguration |
On/Off |
Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration. |
Enable Native PHY Debug Master Endpoint | On/Off |
When you turn this option ON, the transceiver PLL IP core includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for more details. |
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE |
On/Off |
When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled). |
Enable capability registers | On/Off |
Enables capability registers that provide high-level information about the fPLL's configuration. |
Set user-defined IP identifier | Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled. |
|
Enable control and status registers | On/Off |
Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic. |
Configuration file prefix |
Enter the prefix name for the configuration files to be generated. |
|
Generate SystemVerilog package file |
On/Off |
Generates a SystemVerilog package file containing all relevant parameters used by the PLL. |
Generate C header file |
On/Off |
Generates a C header file containing all relevant parameters used by the PLL. |
Generate MIF (Memory Initialize File) |
On/Off |
Generates a MIF file that contains the current configuration. Use this option for reconfiguration purposes in order to switch between different PLL configurations. |
Clock Switchover Parameter | Range | Description |
---|---|---|
Create a second input clock pllrefclk1 | On/Off |
Turn on this parameter to have a backup clock attached to your fPLL that can switch with your original reference clock |
Second Reference Clock Frequency | User Defined |
Specifies the second reference clock frequency for fPLL |
Switchover Mode | Automatic Switchover Manual Switchover Automatic Switchover with Manual Override |
Specifies how Input frequency switchover is handled. Automatic Switchover uses built in circuitry to detect if one of your input clocks has stopped toggling and switch to the other. Manual Switchover creates an EXTSWITCH signal which can be used to manually switch the clock by asserting high for at least 3 cycles. Automatic Switchover with Manual Override acts as Automatic Switchover until the EXTSWITCH goes high, in which case it switches and ignores any automatic switches as long as EXTSWITCH stays high. |
Switchover Delays | 0 to 7 |
Adds a specific amount of cycle delay to the Switchover Process. |
Create an active_clk signal to indicate the input clock in use | On/Off |
This parameter creates an output that indicates which input clock is currently in use by the PLL. Low indicates refclk, High indicates refclk1. |
Create a clkbad signal for each of the input clocks | On/Off |
This parameter creates two clkbad outputs, one for each input clock. Low indicates the CLK is working, High indicates the CLK is not working. |
Parameter | Direction | Description |
---|---|---|
Generates parameter documentation file | On/Off | Generates a .csv file that contains descriptions of all the fPLL parameters and values. |
Port | Direction | Clock Domain | Description |
---|---|---|---|
pll_powerdown |
input |
Asynchronous |
Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel FPGA IP). |
pll_refclk0 |
input |
N/A |
Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter. |
pll_refclk1 |
input |
N/A |
Reference clock input port 1. |
pll_refclk2 |
input |
N/A |
Reference clock input port 2. |
pll_refclk3 |
input |
N/A |
Reference clock input port 3. |
pll_refclk4 |
input |
N/A |
Reference clock input port 4. |
tx_serial_clk |
output |
N/A |
High speed serial clock output port for GX channels. Represents the x1 clock network. |
pll_locked |
output |
Asynchronous |
Active high status signal which indicates if PLL is locked. |
hssi_pll_cascade_clk |
output |
N/A |
fPLL cascade clock output port |
pll_pcie_clk |
output |
N/A |
Used for PCIe. |
reconfig_clk0 |
input |
N/A |
Optional Avalon® interface clock. Used for PLL reconfiguration. |
reconfig_reset0 |
input |
reconfig_clk0 |
Used to reset the Avalon® interface. Asynchronous to assertion and synchronous to deassertion. |
reconfig_write0 |
input |
reconfig_clk0 |
Active high write enable signal. |
reconfig_read0 |
input |
reconfig_clk0 |
Active high read enable signal. |
reconfig_address0[9:0] |
input |
reconfig_clk0 |
10-bit address bus used to specify address to be accessed for both read and write operations. |
reconfig_writedata0[31:0] |
input |
reconfig_clk0 |
32-bit data bus. Carries the write data to the specified address. |
reconfig_readdata0[31:0] |
output |
reconfig_clk0 |
32-bit data bus. Carries the read data from the specified address. |
reconfig_waitrequest0 |
output |
reconfig_clk0 |
Indicates when the Avalon® interface signal is busy. When asserted, all inputs must be held constant. |
pll_cal_busy |
output |
Asynchronous |
Status signal which is asserted high when PLL calibration is in progress. Perform logical OR with this signal and the tx_cal_busy port on the reset controller IP. |
mcgb_rst |
input |
Asynchronous |
Master CGB reset control. Deassert this reset at the same time as pll_powerdown . |
tx_bonding_clocks[5:0] |
output |
N/A |
Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. Used for channel bonding, and represents the x6/xN clock network. |
mcgb_serial_clk |
output |
N/A |
High speed serial clock output for x6/xN non-bonded configurations. |
pcie_sw[1:0] |
input |
Asynchronous |
2-bit rate switch control input used for PCIe protocol implementation. |
pcie_sw_done[1:0] |
output |
Asynchronous |
2-bit rate switch status output used for PCIe protocol implementation. |
fpll_to_fpll_cascade_clk | output |
N/A |
fPLL to fPLL cascade output port (only in Core mode) |
active_clk | output |
N/A |
Creates an output signal that indicates the input clock being used by the PLL. A logic Low on this signal indicates refclk0 is being used and a logic High indicates refclk1 is being used (only in Core mode with Clock Switchover enabled) |
outclk0 |
output |
N/A |
Core output clock 0. (only in Core mode) |
ext_lock_detect_clklow 56 |
output |
N/A |
Clklow output for external lock detection. It can be exposed by selecting the Enable clklow and fref port. |
ext_lock_detect_fref 56 |
output |
N/A |
Fref output for external lock detection It can be exposed by selecting the Enable clklow and fref port. |