Visible to Intel only — GUID: nik1398707190694
Ixiasoft
Visible to Intel only — GUID: nik1398707190694
Ixiasoft
6. Reconfiguration Interface and Dynamic Reconfiguration
Dynamic reconfiguration is the process of dynamically modifying transceiver channels and PLLs to meet changing requirements during device operation. Arria® 10 transceiver channels and PLLs are fully customizable, allowing a system to adapt to its operating environment. You can customize channels and PLLs by dynamically triggering reconfiguration during device operation or following power-up. Dynamic reconfiguration is available for Arria® 10 Transceiver Native PHY, fPLL, ATX PLL, and CMU PLL IP cores.
Use the reconfiguration interface to dynamically change the transceiver channel or PLL settings for the following applications:
- Fine tuning signal integrity by adjusting TX and RX analog settings
- Enabling or disabling transceiver channel blocks, such as the PRBS generator and the checker
- Changing data rates to perform auto negotiation in CPRI, SATA, or SAS applications
- Changing data rates in Ethernet (1G/10G) applications by switching between standard and enhanced PCS datapaths
- Changing TX PLL settings for multi-data rate support protocols such as CPRI
- Changing RX CDR settings from one data rate to another
- Switching between multiple TX PLLs for multi-data rate support
The Native PHY and Transmit PLL IP cores provide the following features that allow dynamic reconfiguration:
- Reconfiguration interface
- Configuration files
- Feature to add PMA analog settings (optional) to the Configuration files (Native PHY only)
- Multiple reconfiguration profiles (Native PHY and ATX PLL)
- Embedded reconfiguration streamer (Native PHY and ATX PLL)
- Native PHY Debug Master Endpoint (NPDME)
- Optional reconfiguration logic
Section Content
Reconfiguring Channel and PLL Blocks
Interacting with the Reconfiguration Interface
Configuration Files
Multiple Reconfiguration Profiles
Embedded Reconfiguration Streamer
Arbitration
Recommendations for Dynamic Reconfiguration
Steps to Perform Dynamic Reconfiguration
Direct Reconfiguration Flow
Native PHY IP or PLL IP Core Guided Reconfiguration Flow
Reconfiguration Flow for Special Cases
Changing PMA Analog Parameters
Ports and Parameters
Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks
Embedded Debug Features
Using Data Pattern Generators and Checkers
Timing Closure Recommendations
Unsupported Features
Arria 10 Transceiver Register Map
Reconfiguration Interface and Dynamic Revision History