F-Tile Interlaken Intel® FPGA IP Release Notes

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ID 683610
Date 7/08/2024
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1. F-Tile Interlaken Intel® FPGA IP Release Notes
1. F-Tile Interlaken Intel® FPGA IP Release Notes x
1.1. F-Tile Interlaken Intel® FPGA IP v8.1.0 1.2. F-Tile Interlaken Intel® FPGA IP v8.0.0 1.3. F-Tile Interlaken Intel® FPGA IP v7.1.0 1.4. F-Tile Interlaken Intel® FPGA IP v7.0.0 1.5. F-Tile Interlaken Intel® FPGA IP v6.1.0 1.6. F-Tile Interlaken Intel® FPGA IP v6.0.0 1.7. F-Tile Interlaken Intel® FPGA IP v5.0.0 1.8. F-Tile Interlaken Intel® FPGA IP v4.1.0 1.9. F-Tile Interlaken Intel® FPGA IP v4.0.0 1.10. F-Tile Interlaken Intel® FPGA IP v3.1.0 1.11. F-Tile Interlaken Intel® FPGA IP v3.0.0 1.12. F-Tile Interlaken Intel® FPGA IP v2.0.0 1.13. F-Tile Interlaken Intel® FPGA IP User Guide Archives 1.14. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
1. F-Tile Interlaken Intel® FPGA IP Release Notes

1.10. F-Tile Interlaken Intel® FPGA IP v3.1.0

Table 10.  v3.1.0 2022.01.14
Quartus® Prime Pro Edition Version Description Impact
21.4 Added the Interlaken Look-aside mode support for following configurations:
  • 12 x 12.5G
  • 12 x 25.78125G
  • 6 x 53.125G
 —
Added support for the following combinations of number of lanes and data rates:
  • 2 x 53.125G
  • 4 x 53.125G
 —
Added new parameters:
  • Enable Interlaken Look-aside mode
  • Enable debug endpoint for Datapath and PMA Avalon memory-mapped interface
—
Added hardware support for the F-tile Interlaken Intel FPGA IP Design Example. —
Added support for Cadence* Xcelium* simulator. —
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