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1.1. F-Tile Interlaken Intel® FPGA IP v8.1.0
1.2. F-Tile Interlaken Intel® FPGA IP v8.0.0
1.3. F-Tile Interlaken Intel® FPGA IP v7.1.0
1.4. F-Tile Interlaken Intel® FPGA IP v7.0.0
1.5. F-Tile Interlaken Intel® FPGA IP v6.1.0
1.6. F-Tile Interlaken Intel® FPGA IP v6.0.0
1.7. F-Tile Interlaken Intel® FPGA IP v5.0.0
1.8. F-Tile Interlaken Intel® FPGA IP v4.1.0
1.9. F-Tile Interlaken Intel® FPGA IP v4.0.0
1.10. F-Tile Interlaken Intel® FPGA IP v3.1.0
1.11. F-Tile Interlaken Intel® FPGA IP v3.0.0
1.12. F-Tile Interlaken Intel® FPGA IP v2.0.0
1.13. F-Tile Interlaken Intel® FPGA IP User Guide Archives
1.14. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
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1. F-Tile Interlaken Intel® FPGA IP Release Notes
The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Section Content
F-Tile Interlaken Intel FPGA IP v8.1.0
F-Tile Interlaken Intel FPGA IP v8.0.0
F-Tile Interlaken Intel FPGA IP v7.1.0
F-Tile Interlaken Intel FPGA IP v7.0.0
F-Tile Interlaken Intel FPGA IP v6.1.0
F-Tile Interlaken Intel FPGA IP v6.0.0
F-Tile Interlaken Intel FPGA IP v5.0.0
F-Tile Interlaken Intel FPGA IP v4.1.0
F-Tile Interlaken Intel FPGA IP v4.0.0
F-Tile Interlaken Intel FPGA IP v3.1.0
F-Tile Interlaken Intel FPGA IP v3.0.0
F-Tile Interlaken Intel FPGA IP v2.0.0
F-Tile Interlaken Intel FPGA IP User Guide Archives
F-Tile Interlaken Intel FPGA IP Design Example User Guide Archives