DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 9/02/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features 2.4. Enabling Adaptive Sync Support 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameter 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features x
2.3.1. Intel® Cyclone® 10 GX DisplayPort SST TX-only Design Features 2.3.2. Intel® Cyclone® 10 GX DisplayPort SST RX-only Design Features
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.9. Simulation Testbench

The simulation testbench simulates the DisplayPort TX serial loopback to RX.
Figure 13.  DisplayPort Intel® FPGA IP Simplex Mode Simulation Testbench Block Diagram
Table 22.  Testbench Components
Component Description
Video Pattern Generator This generator produces color bar patterns that you can configure. You can parameterize the video format timing.
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX core.

The testbench control block also reads the CRC value from both source and sink to make comparisons.
RX Link Speed Clock Frequency Checker This checker verifies if the RX transceiver recovered clock frequency matches the desired data rate.
TX Link Speed Clock Frequency Checker This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate.

The simulation testbench does the following verifications:

Test Criteria Verification
  • Link Training sweep across all data rates from HBR3 to HBR2 to HBR and RBR
  • Read the DPCD registers to check if the DP Status sets and measures both TX and RX Link Speed frequency.
 Integrates Frequency Checker to measure the Link Speed clock's frequency output from the TX and RX transceiver.
  • Run video pattern from TX to RX.
  • Verify the CRC for both source and sink to check if they match.
  • Connects video pattern generator to the DisplayPort Source to generate the video pattern.
  • Testbench control next reads out both Source and Sink CRC from DPTX and DPRX registers and compares to ensure both CRC values are identical.
    Note: To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
A successful simulation ends with the following message:
Table 23.  DisplayPort Design Example Supported EDA Simulators
Simulator Supported Platform Supported Language
Riviera-PRO* Windows/Linux VHDL and Verilog HDL
ModelSim* Windows/Linux VHDL and Verilog HDL
Xcelium* Parallel Linux Verilog HDL
VCS* / VCS* MX Linux VHDL and Verilog HDL
Level Two Title