DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 9/02/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features 2.4. Enabling Adaptive Sync Support 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameter 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features x
2.3.1. Intel® Cyclone® 10 GX DisplayPort SST TX-only Design Features 2.3.2. Intel® Cyclone® 10 GX DisplayPort SST RX-only Design Features
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.3.2. Intel® Cyclone® 10 GX DisplayPort SST RX-only Design Features

This RX-only design example demonstrates the transmission of a single video stream from DisplayPort sink with Pixel CLock Recovery (PCR).
Figure 11.  Intel® Cyclone® 10 GX DisplayPort SST RX-only
  • To generate this RX-only variant, turn on the DisplayPort sink RX SUPPORT DP and the DisplayPort source TX SUPPORT DP parameters.
  • This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source TX SUPPORT IM ENABLE parameter is turned off.
  • The IOPLL drives video clock at a fixed frequency (in this case, 300 MHz by default).
  • If you configure the DisplayPort sink MAX LINK RATE parameter to HBR3 or MAX LINK RATE parameter to HBR2 and PIXELS PER CLOCK to DUAL, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
  • The DisplayPort sink receives video from an external video source such as a GPU and decodes it for the parallel video interface.
  • The design uses the pixel recovery clock (PCR) to recover the pixel clock according to the received MSA information from the sink and converts the RX parallel video interface to the standard VSYNC/HSYNC/DE interface.
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