DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 9/02/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features 2.4. Enabling Adaptive Sync Support 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameter 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features x
2.3.1. Intel® Cyclone® 10 GX DisplayPort SST TX-only Design Features 2.3.2. Intel® Cyclone® 10 GX DisplayPort SST RX-only Design Features
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in the Intel® Quartus® Prime Pro Edition software to generate the design example.
Figure 3. Generating the Design Flow
  1. Click Tools > IP Catalog, and select Intel® Cyclone® 10 GX as the target device family.
    Note: The design example only support Intel® Cyclone® 10 GX devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip .
  4. Select an Intel® Cyclone® 10 GX device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX.
    Note: The Nios II software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios II terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  7. On the Design Example tab, select DisplayPort SST TX-only, DisplayPort SST RX-only, DisplayPort SST Parallel Loopback With PCR, DisplayPort SST Parallel Loopback Without PCR, DisplayPort MST Parallel Loopback With PCR, or DisplayPort MST Parallel Loopback Without PCR.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    Note: DisplayPort MST design examples are supported only in synthesis; they are not supported in simulation.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  9. For Target Development Kit, select Cyclone 10 GX FPGA Development Kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit. For Cyclone 10 GX FPGA Development Kit, the default device is 10CX220YF780E5G..
  10. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.
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