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1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage
2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage
2.2.1.4. Configuration 4: ADC Control Core Only
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core
5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core
5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core
5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core
5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core
5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core
5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core
5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
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1.3. Intel® MAX® 10 ADC Vertical Migration Support
Figure 1. ADC Vertical Migration Across Intel® MAX® 10 DevicesThe arrows indicate the ADC migration paths. The devices included in each vertical migration path are shaded.
Source | Target | Migratable Pins |
---|---|---|
Single ADC device | Single ADC device | You can migrate all ADC input pins |
Dual ADC device | Dual ADC device | |
Single ADC device | Dual ADC device |
|
Dual ADC device | Single ADC device |
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