Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

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ID 683583
Date 3/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide 2. Getting Started 3. Functional Description A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives B. Additional Information
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide x
1.1. Arria 10 Native Fixed Point DSP IP Core Features
2. Getting Started x
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings x
2.1.1. Operation Mode Tab 2.1.2. Pre-adder Tab 2.1.3. Internal Coefficient Tab 2.1.4. Accumulator/Output Cascade Tab 2.1.5. Pipelining Tab 2.1.6. Maximum Input Data Width Per Operation Mode
3. Functional Description x
3.1. Operational Modes 3.2. Optional Modules 3.3. Clocking Scheme 3.4. Arria 10 Native Fixed Point DSP IP Core Signals
3.1. Operational Modes x
3.1.1. The 18 × 18 Full Mode 3.1.2. The 18 × 18 Sum of 2 Mode 3.1.3. The 18 × 18 Plus 36 Mode 3.1.4. The 18 × 18 Systolic Mode 3.1.5. The 27 × 27 Mode
3.1.3. The 18 × 18 Plus 36 Mode x
3.1.3.1. Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode
3.2. Optional Modules x
3.2.1. Input Cascade 3.2.2. Pre-adder 3.2.3. Internal Coefficient 3.2.4. Accumulator and Output Cascade 3.2.5. Pipeline Register
B. Additional Information x
B.1. Arria 10 Native Fixed Point DSP IP Core Document Revision History
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide
2. Getting Started
3. Functional Description
A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives
B. Additional Information

2.1.2. Pre-adder Tab

Table 2.  Pre-adder Tab
Parameter IP Generated Parameter Value Description
‘ay' operand source operand_source_may input preadder Specify the operand source for ay input. Select preadder to enable pre-adder module for top multiplier. Settings for ay and by operand source must be the same.
‘by' operand source operand_source_mby input preadder Specify the operand source for by input. Select preadder to enable pre-adder module for bottom multiplier. Settings for ay and by operand source must be the same.
Set pre-adder a operation to subtraction preadder_subtract_a

No

Yes

Select Yes to specify subtraction operation for pre-adder module for the top multiplier. Pre-adder settings for top and bottom multiplier must be the same.
Set pre-adder b operation to subtraction preadder_subtract_b

No

Yes

Select Yes to specify subtraction operation for pre-adder module for the bottom multiplier. Pre-adder settings for top and bottom multiplier must be the same.
Data 'z' Configuration
'az' input bus width az_width 1–26 Specify the width of az input bus.0
Register input 'az' of the multiplier az_clock

No

Clock0

Clock1

Clock2

Select Clock0 , Clock1 or Clock2 to enable and specify the input clock signal for az input registers. Clock settings for ay, az and bz input registers must be the same.
'bz' input bus width bz_width 1–18 Specify the width of az input bus.0
Register input 'bz' of the multiplier bz_clock

No

Clock0

Clock1

Clock2

Select Clock0 , Clock1 or Clock2 to enable and specify the input clock signal for bz input registers. Clock settings for ay, az and bz input registers must be the same.
Level Two Title