Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

Download PDF
ID 683583
Date 3/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide 2. Getting Started 3. Functional Description A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives B. Additional Information
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide x
1.1. Arria 10 Native Fixed Point DSP IP Core Features
2. Getting Started x
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings x
2.1.1. Operation Mode Tab 2.1.2. Pre-adder Tab 2.1.3. Internal Coefficient Tab 2.1.4. Accumulator/Output Cascade Tab 2.1.5. Pipelining Tab 2.1.6. Maximum Input Data Width Per Operation Mode
3. Functional Description x
3.1. Operational Modes 3.2. Optional Modules 3.3. Clocking Scheme 3.4. Arria 10 Native Fixed Point DSP IP Core Signals
3.1. Operational Modes x
3.1.1. The 18 × 18 Full Mode 3.1.2. The 18 × 18 Sum of 2 Mode 3.1.3. The 18 × 18 Plus 36 Mode 3.1.4. The 18 × 18 Systolic Mode 3.1.5. The 27 × 27 Mode
3.1.3. The 18 × 18 Plus 36 Mode x
3.1.3.1. Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode
3.2. Optional Modules x
3.2.1. Input Cascade 3.2.2. Pre-adder 3.2.3. Internal Coefficient 3.2.4. Accumulator and Output Cascade 3.2.5. Pipeline Register
B. Additional Information x
B.1. Arria 10 Native Fixed Point DSP IP Core Document Revision History
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide
2. Getting Started
3. Functional Description
A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives
B. Additional Information

3.2.1. Input Cascade

Input cascade feature is supported on ay and by input bus. When you set Enable input cascade for 'ay' input to Yes, the Arria 10 Native Fixed Point DSP IP core will take inputs from scanin input signals instead of ay input bus. When you set Enable input cascade for 'by' input to Yes, the Arria 10 Native Fixed Point DSP IP core will take inputs from ay input bus instead of by input bus.

It is recommended to enable the input registers for ay and/or by whenever input cascade is enabled for correctness of application. When you enable the input registers for ay and by, the clock source of these registers must be the same.

You can enable the delay registers to match the latency requirement between the input register and the output register. There are 2 delay registers in the core. The top delay register is used for ay or scanin input ports while the bottom delay register is used for scanout output ports. These delay registers are supported in 18 × 18 full mode, 18 × 18 sum of 2 mode and 18 × 18 systolic mode.

Level Two Title