Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

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ID 683583
Date 3/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide 2. Getting Started 3. Functional Description A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives B. Additional Information
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide x
1.1. Arria 10 Native Fixed Point DSP IP Core Features
2. Getting Started x
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings x
2.1.1. Operation Mode Tab 2.1.2. Pre-adder Tab 2.1.3. Internal Coefficient Tab 2.1.4. Accumulator/Output Cascade Tab 2.1.5. Pipelining Tab 2.1.6. Maximum Input Data Width Per Operation Mode
3. Functional Description x
3.1. Operational Modes 3.2. Optional Modules 3.3. Clocking Scheme 3.4. Arria 10 Native Fixed Point DSP IP Core Signals
3.1. Operational Modes x
3.1.1. The 18 × 18 Full Mode 3.1.2. The 18 × 18 Sum of 2 Mode 3.1.3. The 18 × 18 Plus 36 Mode 3.1.4. The 18 × 18 Systolic Mode 3.1.5. The 27 × 27 Mode
3.1.3. The 18 × 18 Plus 36 Mode x
3.1.3.1. Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode
3.2. Optional Modules x
3.2.1. Input Cascade 3.2.2. Pre-adder 3.2.3. Internal Coefficient 3.2.4. Accumulator and Output Cascade 3.2.5. Pipeline Register
B. Additional Information x
B.1. Arria 10 Native Fixed Point DSP IP Core Document Revision History
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide
2. Getting Started
3. Functional Description
A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives
B. Additional Information

3.4. Arria 10 Native Fixed Point DSP IP Core Signals

The following figure shows the input and output signals of the Arria 10 Native Fixed Point DSP IP core.
Figure 7. Arria 10 Native Fixed Point DSP IP Core Signals
Table 8.  Data Input Signals
Signal Name Type Width Description
ax[] Input 27 Input data bus to top multiplier.
ay[] Input 27 Input data bus to top multiplier.

When pre-adder is enabled, these signals are served as input signals to the top pre-adder.

az[] Input 26

These signals are input signals to the top pre-adder.

These signals are only available when pre-adder is enabled.
bx[] Input 18 Input data bus to bottom multiplier.

These signals are not available in m27×27operational mode.

by[] Input 19 Input data bus to bottom multiplier.

When pre-adder is enabled, these signals serve as input signals to the bottom pre-adder.

These signals are not available in m27×27 operational mode.

bz[] Input 18

These signals are input signals to the bottom pre-adder.

These signals are only available when pre-adder is enabled.

These signals are not available in m27x27 operational mode.

Table 9.  Table: Data Output Signals
Signal Name Type Width Decsription
resulta[] Output 64 Output data bus from top multiplier.

These signals support up to 37 bits for m18×18_full operational mode.

resultb[] Output 37 Output data bus from bottom multiplier.

These signals only available in m18×18_full operational mode.

Table 10.  Table: Clock, Enable and Clear Signals
Signal Name Type Width Description
clk[] Input 3 Input clock signals for all registers.

These clock signals are only available if any of the input registers, pipeline registers or output register is set to Clock0 or Clock1 or Clock2.

  • clk[0] = Clock0
  • clk[1] = Clock1
  • clk[2] = Clock2
ena[] Input 3 Clock enable for clk[2:0].

This signal is active-High.

  • ena[0] is for Clock0
  • ena[1] is for Clock1
  • ena[2] is for Clock2
aclr[] Input 2 Asynchronous clear input signals for all registers.

This signal is active-High.

Use aclr[0] for all input registers and use aclr[1] for all pipeline and output registers.

By default, this signal is de-asserted.
Table 11.  Table: Dynamic Control Signals
Signal Name Type Width Description
sub Input 1 Input signal to add or subtract the output of the top multiplier with the output of the bottom multiplier.
  • Deassert this signal to specify addition operation.
  • Assert this signal to specify subtraction operation.

By default, this signal is deasserted. You can assert or deassert this signal during run-time. 3

negate Input 1 Input signal to add or subtract the sum of top and bottom multipliers with the data from chainin signals.
  • Deassert this signal to specify addition operation.
  • Assert this signal to specify subtraction operation.

By default, this signal is deasserted. You can assert or deassert this signal during run-time.3

accumulate Input 1 Input signal to enable or disable the accumulator feature.
  • Deassert this signal to disable the accumulator feature.
  • Assert this signal to enable the accumulator feature.

By default, this signal is deasserted. You can assert or deassert this signal during run-time.3

loadconst Input 1 Input signal to enable or disable the load constant feature.
  • Deassert this signal to disable the load constant feature.
  • Assert this signal to enable the load constant feature.

By default, this signal is deasserted. You can assert or deassert this signal during run-time.3

Table 12.  Table: Internal Coeficient Signals
Signal Name Type Width Description
coefsela[] Input 3 Input selection signals for 8 coefficient values defined by user for the top multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_a_0 to coef_a_7.
  • coefsela[2:0] = 000 refers to coef_a_0
  • coefsela[2:0] = 001 refers to coef_a_1
  • coelsela[2:0] = 010 refers to coef_a_2
  • ... and so forth.

These signals are only available when the internal coefficient feature is enabled.

coefselb[] Input 3 Input selection signals for 8 coefficient values defined by user for the bottom multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_b_0 to coef_b_7.
  • coefselb[2:0] = 000 refers to coef_b_0
  • coefselb[2:0] = 001 refers to coef_b_1
  • coelselb[2:0] = 010 refers to coef_b_2
  • ... and so forth.

These signals are only available when the internal coefficient feature is enabled.

Table 13.  Table: Input Cascade Signals
Signal Name Type Width Description
scanin[] Input 27 Input data bus for input cascade module.

Connect these signals to the scanout signals from the preceding DSP core.

scanout[] Ouput 27 Output data bus of the input cascade module.

Connect these signals to the scanin signals of the next DSP core.

Table 14.  Table: Output Cascade Signals
Signal Name Type Width Description
chainin[] Input 64 Input data bus for output cascade module.

Connect these signals to the chainout signals from the preceding DSP core.

chainout[] Output 64 Output data bus of the output cascade module.

Connect these signals to the chainin signals of the next DSP core.

3 Do not tie this signal to 0 when the input register or the pipeline register is enabled.
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