E-Tile Hard IP for Ethernet Release Notes

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ID 683582
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. E-Tile Hard IP for Ethernet Release Notes 2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes 3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes 4. E-tile Hard IP User Guide Archives
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes x
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.1.0 2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.0.0 2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0 2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0 2.5. E-Tile Hard IP for Ethernet Intel® FPGA IP v21.0.0 2.6. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.3.0 2.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.1 2.8. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.2.0 2.9. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.4.0 2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0 2.11. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.2 2.12. E-tile Hard IP for Ethernet Intel® FPGA IP v19.1 2.13. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1.1 2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1 2.15. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.0
3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes x
3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.1.0 3.2. E-Tile Ethernet IP for Intel Agilex FPGA v24.0.1 3.3. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0 3.4. E-Tile Ethernet IP for Intel Agilex FPGA v22.0.0 3.5. E-Tile Ethernet IP for Intel Agilex FPGA v21.0.0 3.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.0 3.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1 3.8. E-Tile Ethernet IP for Intel Agilex FPGA v19.4.0 3.9. E-Tile Ethernet IP for Intel Agilex FPGA v19.3.0
1. E-Tile Hard IP for Ethernet Release Notes
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes
3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes
4. E-tile Hard IP User Guide Archives

3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.1.0

Table 18.  v24.1.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Changed Nios® implementation from Nios® II to Nios® V in the E-Tile Dynamic Reconfiguration Design Example. —

Some Intel® FPGA IP products that previously included a Nios® II processor now use a Nios® V processor.

If you do not have a valid Nios® V license, you might receive an error message when you generate programming files for a design that includes these Intel® FPGA IP products.

For details and a workaround, refer to Why do I get an error in generating programming files and it shows as invalid license for Nios® V Processor for Intel® FPGA in the Quartus® Prime Pro Edition software version 24.1? in the Intel® FPGA Knowledge Base.

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