E-Tile Hard IP for Ethernet Release Notes

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ID 683582
Date 4/29/2024
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1. E-Tile Hard IP for Ethernet Release Notes 2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes 3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes 4. E-tile Hard IP User Guide Archives
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes x
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.1.0 2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.0.0 2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0 2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0 2.5. E-Tile Hard IP for Ethernet Intel® FPGA IP v21.0.0 2.6. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.3.0 2.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.1 2.8. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.2.0 2.9. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.4.0 2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0 2.11. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.2 2.12. E-tile Hard IP for Ethernet Intel® FPGA IP v19.1 2.13. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1.1 2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1 2.15. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.0
3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes x
3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.1.0 3.2. E-Tile Ethernet IP for Intel Agilex FPGA v24.0.1 3.3. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0 3.4. E-Tile Ethernet IP for Intel Agilex FPGA v22.0.0 3.5. E-Tile Ethernet IP for Intel Agilex FPGA v21.0.0 3.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.0 3.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1 3.8. E-Tile Ethernet IP for Intel Agilex FPGA v19.4.0 3.9. E-Tile Ethernet IP for Intel Agilex FPGA v19.3.0
1. E-Tile Hard IP for Ethernet Release Notes
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes
3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes
4. E-tile Hard IP User Guide Archives

2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1

Table 16.  v18.1 September 2018
Description Impact
Added support for 10GE/25GE with optional Reed-Solomon Forward Error Correction (RS-FEC) with Auto-Negotiation and Link Training variant up to 4 channels. —
Added support for Auto-Negotiation and Link Training with the following features:
  • Optional RSFEC request during Auto-Negotiation
  • Option to advertise copper cable (CR) or backplane (KR) capability
  • Option to select default lane to perform Auto-Negotiation
  • Option to advertise both 10GE and 25GE capability during Auto-Negotiation
  • Option to enable symmetric and asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015
—
Added support of the following variants for 10GE/25GE:
  • PCS Only
  • Optical Transport Network (OTN)
  • Flexible Ethernet
 —
Added Precision Timestamp Protocol (PTP) for 10GE variant. —
Added 156.250000 MHz PHY Reference Frequency support for 10GE/25GE. —
Added the following PHY Reference Frequency support for 100GE:
  • 322.265625 MHz
  • 312.500000 MHz
  • 644.531250 MHz
 —
Added support for RS-FEC (544,514) coding for 100GE MAC + PCS, PCS only, OTN, and FlexE variants. —
Added simulation and hardware design examples for the following variants:
  • 10GE/25GE/100GE MAC + PCS with optional RS-FEC and PTP
  • 10GE/25GE PCS with optional RS-FEC and PTP
  • 10GE/25GE OTN with optional RS-FEC and PTP
  • 10GE/25GE FlexE with optional RS-FEC and PTP
  • 100GE PCS with optional RS-FEC
  • 100GE OTN with optional RSF-FEC
  • 100GE FlexE with optional RS-FEC
 —
When there are multiple E-Tile for Hard IP Ethernet IP cores with different configurations instantiated in a project, the design may compile incorrectly or may cause fitter error.

You can see compilation warning where settings for modules with the same name are overwritten during Quartus project compilation and design simulation compilation. This may also affect the design functionality in simulation and hardware.

For more information, refer to Warning (16817): Verilog HDL waring at alt_etipc3_nphy_elane.v (12698)

Fitter is unable to place transceivers correctly when more than 1 channel of 10GE/25GE with PTP and RSFEC enabled, due to incorrect channel restrictions.

You can see observed fitter error during compilation. For more information, refer to Why do I get fitter errors when compiling a design with multiple instances of the Intel Stratix 10 E-tile Hard IP for Ethernet Intel FPGA IP, where PTP and RSFEC options have been enabled?.

For 100GE PCS+(528,514)RSFEC and 100GE PCS+(544,514)RSFEC variant, there is no signal to indicate local fault condition in the IP core.

The IP core is not able to detect local fault condition on RX PCS datapath.

For more information, refer to How do I tell the difference between a local fault condition and valid RX data when using the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP configured in PCS+FEC status without the MAC .

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