E-Tile Hard IP for Ethernet Release Notes

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ID 683582
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. E-Tile Hard IP for Ethernet Release Notes 2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes 3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes 4. E-tile Hard IP User Guide Archives
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes x
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.1.0 2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.0.0 2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0 2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0 2.5. E-Tile Hard IP for Ethernet Intel® FPGA IP v21.0.0 2.6. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.3.0 2.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.1 2.8. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.2.0 2.9. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.4.0 2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0 2.11. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.2 2.12. E-tile Hard IP for Ethernet Intel® FPGA IP v19.1 2.13. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1.1 2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1 2.15. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.0
3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes x
3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.1.0 3.2. E-Tile Ethernet IP for Intel Agilex FPGA v24.0.1 3.3. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0 3.4. E-Tile Ethernet IP for Intel Agilex FPGA v22.0.0 3.5. E-Tile Ethernet IP for Intel Agilex FPGA v21.0.0 3.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.0 3.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1 3.8. E-Tile Ethernet IP for Intel Agilex FPGA v19.4.0 3.9. E-Tile Ethernet IP for Intel Agilex FPGA v19.3.0
1. E-Tile Hard IP for Ethernet Release Notes
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes
3. E-Tile Ethernet IP for Agilex™ 7 FPGA Release Notes
4. E-tile Hard IP User Guide Archives

2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0

Table 12.  v19.3.0 2019.09.30
Quartus® Prime Version Description Impact
19.3 10G/25G variant for E-tile Hard IP for Ethernet Intel® FPGA IP:
  • UI adjustment under +/-100ppm condition for 10G/25G variants.
The E-tile Hard IP for Ethernet Intel® FPGA IP provides set of registers to compute the new TX/RX UI under PPM condition.
10G/25G variant for E-tile Hard IP for Ethernet Intel® FPGA IP:
  • Added Ready Latency parameter for 10GE/25GE variants.
Useful when user need to pipeline TX valid signal when facing a timing issue.
IP tab for E-tile Hard IP for Ethernet Intel® FPGA IP:
  • Removed Reconfig clock rate parameter.
—
Added production device kit support:
  • Updated the target development kit option for Stratix® 10 devices from Stratix 10 TX Transceiver Signal Integrity Development Kit to Stratix 10 TX SI Development Kit -1ST280EY2F55E2VGS1 and Stratix 10 TX SI Development Kit -1ST280EY2F55E2VG .
User can select different development kit with different OPN.
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