Visible to Intel only — GUID: xuv1600795342645
Ixiasoft
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.1.0
2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.0.0
2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0
2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0
2.5. E-Tile Hard IP for Ethernet Intel® FPGA IP v21.0.0
2.6. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.3.0
2.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.1
2.8. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.2.0
2.9. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.4.0
2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0
2.11. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.2
2.12. E-tile Hard IP for Ethernet Intel® FPGA IP v19.1
2.13. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1.1
2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1
2.15. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.0
3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.1.0
3.2. E-Tile Ethernet IP for Intel Agilex FPGA v24.0.1
3.3. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0
3.4. E-Tile Ethernet IP for Intel Agilex FPGA v22.0.0
3.5. E-Tile Ethernet IP for Intel Agilex FPGA v21.0.0
3.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.0
3.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1
3.8. E-Tile Ethernet IP for Intel Agilex FPGA v19.4.0
3.9. E-Tile Ethernet IP for Intel Agilex FPGA v19.3.0
Visible to Intel only — GUID: xuv1600795342645
Ixiasoft
3.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1
Quartus® Prime Version | Description | Impact |
---|---|---|
20.3 | Added Preserve Unused Transceiver Channels parameter for 100G Ethernet variants. | When enabled, preserves the unused PAM4 slave channel for selected variants with enabled RS-FEC (544,514) option. |