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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. Multiple 25G Synchronous Ethernet Channels
2.3.6. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.7. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. CPRI Dynamic Reconfiguration Design Examples
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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4.4.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
This section provides a sequential flow for dynamic reconfiguration of 25GbE PTP FEC configuration to 24G CPRI FEC configuration. For other variations, you can refer to the generated C file that provides comprehensive information through comments.
- Assert the i_sl_tx_rst_n and i_sl_rx_rst_n reset signals.
- Disable Serdes (via PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
- Perform switching of reference clock mux:
- Switch PMA controller clock to XCVR_Refclk1.
- Refclk switching from i_clk_ref[0] (156.25MHz) to i_clk_ref [1] (184.32MHz).
- Switch PMA controller clock to XCVR_Refclk0.
Note: Steps a and c are required for hardware test only to avoid potential hardware glitch due to reference clock switch operation. You can skip these steps in simulation.For more information, refer to the E-Tile Transceiver PHY User Guide. - Perform PMA Analog Reset. For more information, refer to the E-Tile Transceiver PHY User Guide.
- Change the following registers:
Table 45. Registers: 25GbE PTP FEC to 24G CPRI FEC Block Configuration Registers Offset From Value To Value ELANE txmac_ehip_cfg 0x40B 0x027E00E0 0x027E01E0 (simulation) 0x9FFE01E0 (hardware)
phy_ehip_pcs_modes 0x30E 0x00000093 0x0000_0083 phy_ehip_mode_muxes 0x30D 0x00000000 0x00000008 tx_data_path_mux 0x350 0x003F1001 0x003F1002 rx_data_path_mux 0x255 0x00000001 0x00000002 RS-FEC rsfec_top_clk_cfg fec_lane_ena [3:0]
0x4C 0x00000000 0x00000003 Transceiver TX Refclk Ratio 0x84 0xA5 0x84 0x85 0 0 0x86 0x5 0x5 0x87 0 0 RX Refclk Ratio 0x84 0xA5 0x84 0x85 0 0 0x86 0x6 0x6 0x87 0 0 - Adjust the phase offset of a recovered clock using the RX Phase Slip (via PMA attribute code 0x000E). For more information, refer to the E-Tile Transceiver PHY User Guide.
- Enable Serdes (via PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
- Enable internal serial loopback (via PMA attribute code 0x0008). For more information, refer to the E-Tile Transceiver PHY User Guide.
- Deassert the i_sl_tx_rst_n and i_sl_rx_rst_n reset signals.
- Wait until:
PIO_OUT[3:0] = 0xF (o_tx_ptp_ready, o_sl_rx_pcs_ready, o_sl_rx_block_lock, o_ehip_ready asserted)
- Send packets for RX CDR deskew training, wait until:
PIO_OUT[4] = 0x1 (o_rx_ptp_raedy asserted)
- Clear ELANE statistic counters.
- Enable packet generator to send 20 packets data.
- Check TX packet count statistic counter to ensure all the packets are sent, then stop packet generator.
- Check for the expected packets to be received by packet checker.
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