E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

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ID 683578
Date 4/29/2024
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Design Examples 2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Stratix® 10 Design Examples User Guide Archives
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench x
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Stratix 10 FPGA
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. Multiple 25G Synchronous Ethernet Channels 2.3.6. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.7. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components 2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. CPRI Dynamic Reconfiguration Design Examples 4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation 4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. CPRI Dynamic Reconfiguration Design Examples x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. CPRI Design Example Interface Signals 4.3.5. CPRI Design Example Registers 4.3.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme
4.3.2. Simulation Design Examples x
4.3.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.3.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. 25G Ethernet to CPRI Design Example Interface Signals 4.4.5. 25G Ethernet to CPRI Design Examples Registers 4.4.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme 4.4.1.2. Reset
4.4.2. Simulation Design Examples x
4.4.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example x
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example 4.5.3.2. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.7. Steps to Enable FEC x
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)] 4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)] 4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
1. About E-tile Hard IP Design Examples
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Stratix® 10 Design Examples User Guide Archives

4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example

Document Version Quartus® Prime Version IP Version Changes
2024.04.29 24.1 21.0.0 Made the following changes due to Nios® II to Nios® V migration:
  • Corrected the 10G/25G Ethernet and 25G Ethernet to CPRI Design Example Directory Structure diagram.
  • Corrected the title "Running the Simulation with Default HEX File" to Running the Simulation.
  • Updated the topic Running the Simulation due to Nios® II to Nios® V migration.
  • Corrected the title "Running the Simulation with New HEX File to Generating New Hex File using Eclipse-based Ashling RiscFree IDE Tool
  • Updated the Generating New Hex File using Eclipse-based Ashling RiscFree IDE Tool topic.
  • Corrected " Nios® II Software Build Tools (SBT) for Eclipse" to Eclipse-based Ashling RiscFree IDE Tool.
  • Updated the topic Running the Design Example in Hardware in Testing the E-Tile Dynamic Reconfiguration Design Example Testbench.
  • Corrected Nios® II to Nios® V in the following block diagrams:
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with RS-FEC Dynamic Reconfiguration Design Example
    • Simulation Block Diagram for 9.8G CPRI PHY Dynamic Reconfiguration Design Example
  • Corrected " Nios® II Software Build Tools (SBT) for Eclipse" to Eclipse-based Ashling RiscFree IDE Tool in CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components.
  • Corrected Nios® II to Nios® V in Simulation Block Diagram for 25G Ethernet to CPRI Dynamic Reconfiguration Design Example.
2023.04.10 22.4 20.4.0
  • Added the following information in 100G Ethernet Dynamic Reconfiguration Design Example.
    • When a CSR reset occurs during or after a dynamic reconfiguration transition(DR), you must first perform a DR transition to the base operation mode. Failure to complete this step may result in errors during the DR transition to other supported configurations.
2022.09.26 22.3 20.4.0 Made the following updates:
  • Added registers to the "100G Ethernet Dynamic Reconfiguration Registers" table in the 100G Ethernet Dynamic Reconfiguration Examples Registers section
  • Added additional information regarding 100G Ethernet Dynamic Reconfiguration Design Example with internal and external CPU.
  • Added the Additional Reconfig Options in Quartus® Prime Pro Edition software v22.2 for Stratix® 10 E-tile section
  • Added support for the following in 100G Ethernet Dynamic Reconfiguration Design Examples:
    • 100G MAC+PCS+(544,514)RS-FEC [PAM4]
    • 100G MAC+PCS+(544,514)RS-FEC [NRZ]
2022.03.06 21.3 20.3.0 Updated directory paths in the following sections:
  • Running the Simulation with Default HEX File
  • Running the Simulation with New HEX File
2021.11.22 21.3 20.3.0
  • Added support for QuestaSim* simulator.
  • Removed support for NCSim simulator.
  • Added new sections:
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
    • Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
    • Steps to Enable FEC
    • Steps to Disable FEC
2021.08.11 21.2 20.3.0 Added support for the following in 25G Ethernet to CPRI Dynamic Reconfiguration Design Example:
  • Tunneling mode for CPRI protocol.
  • Dynamic reconfiguration transition to 1G Ethernet.
2021.04.28 20.4 20.3.0 Added a Table: CPRI PHY Soft Configuration Register Space in section: 10GE/25GE Design Examples Registers.
2020.12.14 20.4 20.3.0
  • Added 1GE with PTP variant support for for 25GE with RS-FEC and PTP base operation and 1GE variant support for 25GE with RS-FEC in the 10G/25G Ethernet Dynamic Reconfiguration Design Examples section.
  • Updated following figures in Clocking Scheme section:
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
  • Updated following diagrams in Simulation Design Examples section:
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with RS-FEC Dynamic Reconfiguration Design Example
  • Made following changes in sections 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components and 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components:
    • Added description for new blocks.
    • Updated sample output test results.
  • Updated Table: E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Examples Register Map with Triple-Speed Ethernet registers.
  • Added following tables in 10GE/25GE Design Examples Registers section:
    • Table: 1GE Packet Generator Registers
    • Table: 1GE Traffic Monitor Registers
2020.06.29 20.2 20.2.0
  • Added support for dynamic reconfiguration (DR) transitions from high speed CPRI protocol to low PMA-D modes in 25G Ethernet to CPRI Dynamic Reconfiguration Design Example:
    • 24G CPRI with RS-FEC to 10G CPRI
    • 10G CPRI to 9.8G CPRI
    • 9.8G CPRI to 4.9G CPRI
    • 4.9G CPRI to 2.4G CPRI
    • 2.4G CPRI to 24G CPRI with RS-FEC

    Updated DR simulation test sequence and DR hardware test GUI display with the added transitions.

  • Added dl_reset signal in the CPRI PHY Soft Registers table. The reset acts as a soft reset to the deterministic latency block.
2020.04.13 20.1 20.1.0
  • Added support for deterministic latency feature in the 25G Ethernet to CPRI protocol.
    • Updated the Clocking Scheme for 24G CPRI with RS-FEC Dynamic Reconfiguration Design Example figure.
    • Updated the Simulation Block Diagram for 25G Ethernet to CPRI Dynamic Reconfiguration Design Example figure.
    • Updated components described in the 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components section.
    • Added CPRI PHY soft registers table in the 25G Ethernet to CPRI Design Examples Registers section.
  • Updated Clock Control frequency setting in the Testing the E-tile Dynamic Reconfiguration Hardware Design Example section. This setting applies to CPRI and Ethernet to CPRI protocols.
  • Updated TEST_MODE selection in the 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components section. TEST_MODE options are 0, 1, and 2.
2019.12.23 19.4 19.4.0
  • Added simulation, compilation, and timing support for Stratix® 10 dynamic reconfiguration design examples:
    • 9.8G CPRI with direct PMA
    • 100G Ethernet
  • Restructured topics to improve the content flow.
2019.09.30 19.3 19.3.0
  • Added List of Supported Dynamic Reconfiguration Design Example variants table.
  • Added a note to clarify run_vcs.sh and run_vcsmx.sh usage in the Steps to Simulate the Testbench table.
  • Updated Running the Design Example in Hardware section:
    • Added the board control configuration step
    • Added screenshot of a successful hardware test
  • Updated Power Management Setting for Stratix® 10 E-tile TX Transceiver Signal Integrity Development Kit section.
  • Added Note: i_channel_PLL is E-tile Transceiver PHY specific signal that utilizes additional transceiver E-tile channel. in the Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example figure.
  • Updated test run sequence in the 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components section.
  • Replaced clk_100 with clk100 in clocking scheme figures:
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
    • Clocking Scheme for CPRI with RS-FEC Dynamic Reconfiguration Design Example
  • Added the Calibration Flow for the Hardware Test Script section for all dynamic reconfiguration variants.
  • Added screenshot of the Dynamic Reconfiguration Hardware test for all dynamic reconfiguration variants.
  • Updated Dynamic Reconfiguration Design Example Components sections to include the following steps in the DR tests. Updates are applicable to all DR variants.
    • Disabling SERDES.
    • Triggering PMA analog reset.
    • Adjusting the phase offset of a recovered clock.
    • Enabling SERDES.
19.2.0
  • Added variants: 24G CPRI, 9.8G CPRI, 4.9G CPRI, and 2.4G CPRI in CPRI Dynamic Reconfiguration Design example.
  • Added 25G Ethernet to CPRI Dynamic Reconfiguration simulation, compilation-only project, and hardware design examples.
  • Updated directory structure in E-tile Dynamic Reconfiguration 10G/25G Ethernet and 25G Ethernet to CPRI Design Example Directory Structure and E-tile Dynamic Reconfiguration CPRI With and Without RS-FEC Design Example Directory Structure figures:
    • Added flow.c in software/dynamic_reconfiguration_hardware.
    • Added c3_function.c file in software/dynamic_reconfiguration_hardware and software/dynamic_reconfiguration_sim.
    • Renamed c3_config.c file with c3_recconfig.c in software/dynamic_reconfiguration_hardware and software/dynamic_reconfiguration_sim.
    • Renamed c3_config.h file with c3_recconfig.h file in software/dynamic_reconfiguration_hardware and software/dynamic_reconfiguration_sim.
    • Added cadence and xcelium folders in example_testbench.
    • Renamed eth_25g_pma_direct folder with eth_25g_channel_pll in hardware_test_design.
    • Added reset_release folder in hardware_test_design.
    • Added reset_release.ip file in the hardware_test_design.
  • Added c3_function.c and flow.c functions to dynamic_reconfiguration_sim and dynamic_reconfiguration_hardware directories.
  • Added Ethernet to CPRI Protocol in the E-tile Dynamic Reconfiguration Design Example: Generating the Design section.
  • Added Xcelium* and NCSim simulators support.
  • Renamed 10G/24G CPRI with CPRI globally.
  • Added cpu_resetn and updated i_clk_ref signal's description in the 10GE/25GE Design Example Interface Signals section.
  • Added test cases in the CPRI Protocol reconfiguration flow section.
    • 24G CPRI with RS-FEC to 24G CPRI without RS-FEC
    • 24G CPRI without RS-FEC to 10G CPRI
    • 10G CPRI to 24G CPRI without RS-FEC
    • 24G CPRI without RS-FEC to 24G CPRI with RS-FEC
    • 10G CPRI to 9.8G CPRI
    • 9.8G CPRI to 4.9G CPRI
    • 4.9G CPRI to 2.4G CPRI
  • Updated phy_ref_clk to phy_ref_clk[1:0] signal in the Simulation Block Diagram for CPRI PHY with RS-FEC Dynamic Reconfiguration Design Example figure.
  • Updated bit size to i_clk_ref_cpri[1:0] in the CPRI Hardware Dynamic Reconfiguration Design Example Interface Signals table.
2019.05.17 19.1 19.1 Initial release.
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