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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. Multiple 25G Synchronous Ethernet Channels
2.3.6. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.7. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. CPRI Dynamic Reconfiguration Design Examples
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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4.3.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
The 24G CPRI PHY hardware dynamic reconfiguration design example and 9.8G CPRI PHY hardware dynamic reconfiguration design example include the following components:
- E-tile CPRI PHY Intel® FPGA IP core.
- E-tile CPRI PHY Intel® FPGA IP core - 24G CPRI
- E-tile CPRI PHY Intel® FPGA IP core - 9.8G CPRI PMA direct mode
- XGMII packet generator and checker that coordinates the programming of the IP core and packet generation.
Note: This component is only available for 24G CPRI variant.
- 8B/10B pattern generator and checker that coordinates the programming of the IP core and packet generation.
- Avalon® memory-mapped interface address decoder to decode reconfiguration address space for E-tile CPRI PHY Intel® FPGA IP core, transceiver, and RS-FEC modules during reconfiguration accesses.
- Nios® V System that communicates with the Eclipse-based Ashling RiscFree IDE Tool. You communicate with the client logic and E-Tile Hard IP for Ethernet Intel FPGA IP through the tool.
- Native PHY in PMA Direct mode that acts as a channel PLL to provide EMIB clocks (for example, 402.8 MHz and 805.6 MHz), as required by the E-tile CPRI PHY Intel® FPGA IP core.
- IOPLL to provide sampling clock (for example, 250 MHz for E-tile CPRI PHY Intel® FPGA IP core) and round-trip (RT) counter.
- Sources and Probes module to measure the round-trip value of the E-tile CPRI PHY Intel® FPGA IP core in all supported speed modes.
The following sample outputs illustrate a successful hardware test run for a 24G CPRI PHY with RS-FEC IP core variation:
CPU is alive! Dynamic Reconfiguration Hardware Test By default, the starting mode is CPRI24G_FEC. Please choose the Targeted mode available: 1) CPRI24G 2) CPRI12GFEC 3) CPRI12G 4) CPRI10GFEC 5) CPRI10G 6) CPRI9.8G 7) CPRI6.0G 8) CPRI4.9G 9) CPRI3.0G a) CPRI2.4G 9) Terminate test -> If you terminate test halfway, you must reload the .sof file before retrigger the hardware test. Enter a Valid Selection: