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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. Multiple 25G Synchronous Ethernet Channels
2.3.6. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.7. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. CPRI Dynamic Reconfiguration Design Examples
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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4.4.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
The 25G Ethernet to CPRI hardware dynamic reconfiguration design example includes the following components:
- E-Tile Hard IP for Ethernet Intel FPGA IP core.
- Client 10G/25G logic that coordinates the programming of the IP core and packet generation.
- Client XGMII Pattern Generator and Checker that coordinates the programming of the IP core and packet generation.
- Client 8B/10B Pattern Generator and Checker that coordinates the programming of the IP core and packet generation.
- Round trip counter to measure the total round trip delay value via the DUT.
- IO PLL to provide sampling clock, 250 MHz for DUT and the Round trip counter.
- Time-of-day (ToD) module to provide a continuous flow of current time-of-day information to the IP core.
- PIO block to store RX and TX PTP timestamp for accuracy calculation and to send PTP 2-step timestamp request.
- Avalon® -MM address decoder to decode reconfiguration address space for MAC, transceiver, and RS-FEC modules during reconfiguration accesses.
- Nios® V System that communicates with the Eclipse-based Ashling RiscFree IDE Tool. You communicate with the client logic and E-Tile Hard IP for Ethernet Intel FPGA IP through the tool.
- Triple-Speed Ethernet Intel FPGA IP core.
- Time-of-day (ToD) master module provides a continuous flow of current time-of-day information to Triple-Speed Ethernet Intel FPGA IP core.
- Ethernet 1G packet generator and monitor for Triple-Speed Ethernet IP core (generate ‘n’ number of packets to transmit and check ‘n’ number of packets received).
- 32B packet generator and checker that handles the packet generation for the Tunneling Mode feature in CPRI PHY IP core.
When switching from Ethernet to CPRI protocol mode, the CPRI PHY Soft wrapper module reads the TX and RX datapath latency and Round trip counter values and displays them in the dynamic reconfiguration hardware test. For more information about CPRI PHY registers, refer to the E-tile Hard IP User Guide: E-Tile CPRI PHY Intel FPGA IP section.
The following sample outputs illustrate a successful hardware test run for a 25GE, MAC+PCS, RS-FEC, with PTP IP core variation:
CPU is alive! Dynamic Reconfiguration Hardware Test By default, the starting mode is 25G_PTP_RSFEC. Please choose one of Dynamic reconfiguration: 0) 25G_PTP_RSFEC -> 10G_PTP -> 25G_PTP_RSFEC -> CPRI_24G_RSFEC -> 25G_PTP_RSFEC -> CPRI_10G -> 25G_PTP_RSFEC -> CPRI_9p8G -> 25G_PTP_RSFEC -> CPRI_4p9G -> 25G_PTP_RSFEC -> CPRI_2p4G -> 25G_PTP_RSFEC 1) 25G_PTP_RSFEC -> CPRI_24G_RSFEC 2) CPRI_24G_RSFEC -> 25G_PTP_RSFEC 3) 25G_PTP_RSFEC -> CPRI_10G 4) CPRI_10G -> 25G_PTP_RSFEC 5) 25G_PTP_RSFEC -> CPRI_9p8G 6) CPRI_9p8G -> 25G_PTP_RSFEC 7) 25G_PTP_RSFEC -> CPRI_4p9G 8) CPRI_4p9G -> 25G_PTP_RSFEC 9) 25G_PTP_RSFEC -> CPRI_2p4G a) CPRI_2p4G -> 25G_PTP_RSFEC b) CPRI_24G_RSFEC -> CPRI_10G c) CPRI_10G -> CPRI_9p8G d) CPRI_9p8G -> CPRI_4p9G e) CPRI_4p9G -> CPRI_2p4G f) CPRI_2p4G -> CPRI_24G_RSFEC g) 25G_PTP_RSFEC -> 10G_PTP h) 10G_PTP -> 25G_PTP_RSFEC i_ 25G_PTP_RSFEC -> CPRI_24G_RSFEC -> CPRI_10G -> CPRI_9p8G -> CPRI_4p9G -> CPRI_2p4G -> CPRI_24G_RSFEC -> 25G_PTP_RSFEC j) Terminate test If you terminate the test halfway, you must reload the .sof file before retrigger the hardware test. Enter a Valid Selection (0,1,3,5,7,9,g,i,j): 0 You entered: 0. Execute five pairs of dynamic reconfiguration. INFO: Dynamic reconfiguration: 25G_PTP_RSFEC -> 10G_PTP INFO: End of dynamic reconfiguration: 25G_PTP_RSFEC -> 10G_PTP INFO: PKT_RX_CNT received = 20 INFO: Dynamic reconfiguration: 25G_PTP_RSFEC -> CPRI_24G_RSFEC INFO: End of dynamic reconfiguration: 25G_PTP_RSFEC -> CPRI_24G_RSFEC INFO: tx_delay info: 26fb INFO: rx_delay info: 7908 INFO: 24G with FEC rx bitslip value info: 4c INFO: Total Output RT count value (sample sizes: hardware: 128, sim: 32): 5115 Test Pass!