Visible to Intel only — GUID: ows1574224095911
Ixiasoft
Visible to Intel only — GUID: ows1574224095911
Ixiasoft
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example
- 100G Ethernet as DR Protocol.
- Under the 100G Ethernet Protocol tab:
- 100G Ethernet MAC+PCS RS-FEC as DR Design.
- Internal as DR Controller Location.
- Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit as the target development kit.
Refer to the simulation instructions content in the Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench section. The steps are applicable for 100G Ethernet MAC+PCS with optional RS-FEC variant.
The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.
To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The standard specifies an alignment marker interval of 16,384 words in each virtual lane. The simulation model with the testbench implements an alignment marker interval of 512 words.
In order to run simulation with the IEEE Ethernet standard specified interval, refer to Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example for more information.
The successful test run displays output confirming the following behavior:
- The client logic resets the IP core.
- Waits for RX datapath to align.
- Once alignment is complete, client logic transmits a series of packets to the IP core.
- The client logic receives the same series of packets through RX MAC interface.
- The client logic then checks the number of packets received and verify that the data matches with the transmitted packets.
- Displaying Testbench complete.
The following sample output illustrates a portion of successful simulation test run for a 100GE, MAC+PCS without RS-FEC IP core variation.
# o_tx_lanes_stable is 1 at time 348403500 # waiting for tx_dll_lock.... # TX DLL LOCK is 1 at time 407396143 # waiting for tx_transfer_ready.... # TX transfer ready is 1 at time 407716015 # waiting for rx_transfer_ready.... # RX transfer ready is 1 at time 418791583 # EHIP PLD Ready out is 1 at time 418848000 # EHIP reset out is 0 at time 418992000 # EHIP reset ack is 0 at time 419070847 # EHIP TX reset out is 0 at time 419416000 # EHIP TX reset ack is 0 at time 470466959 # waiting for EHIP Ready.... # EHIP READY is 1 at time 470536467 # EHIP RX reset out is 0 at time 472496000 # waiting for rx reset ack.... # EHIP RX reset ack is 0 at time 472509994 # Waiting for RX Block Lock # EHIP RX Block Lock is high at time 503401281 # Waiting for AM lock # EHIP RX AM Lock is high at time 503401281 # Waiting for RX alignment 503401281 # RX deskew locked 503403000 # RX lane aligmnent locked # ** Sending Packet 1... # ... # ** Received Packet 10... # # DR -> 100G NoFEC # ** DR STARTING # # ===> writedata = 00000000 # ===> writedata = 000000020 # ===> writedata = 00010000 # ===> writedata = 00000001 # # ** RECONFIG CALLED, WAITING FOR DR # # ===>MATCH! ReaddataValid = 1 Readdata = 00000001 Expected_Readdata = 00000001 # ===>AVMM READ MISMATCH! ReaddataValid = 1 Readdata = 00000001 Expected_Readdata = 00000000 # ===>MATCH! ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 000000000 # # Reconfig Done # # ** RECONFIG DONE # # waiting for o_tx_lanes_stable... # o_tx_lanes_stable is 1 at time 804564000 # waiting for tx_dll_lock.... # TX DLL LOCK is 1 at time 804564000 # waiting for tx_transfer_ready.... # TX transfer ready is 1 at time 804564000 # waiting for rx_transfer_ready.... # RX transfer ready is 1 at time 808135783 # EHIP PLD Ready out is 1 at time 808135783 # EHIP reset out is 0 at time 808135883 # EHIP reset ack is 0 at time 808135883 # EHIP TX reset out is 0 at time 808632000 # EHIP TX reset ack is 0 at time 808645131 # waiting for EHIP Ready.... # EHIP READY is 1 at time 808754358 # EHIP RX reset out is 0 at time 810672000 # waiting for rx reset ack.... # EHIP RX reset ack is 0 at time 810685684 # Waiting for RX Block Lock # EHIP RX Block Lock is high at time 813021645 # Waiting for AM lock # EHIP RX AM Lock is high at time 814548336 # Waiting for RX alignment 814548336 # RX deskew locked 815377000 # RX lane aligmnent locked # ** Sending Packet 1... # ... # ** Received Packet 10... # ** # ** Testbench complete. # ** # *****************************************