Intel® FPGA Programmable Acceleration Card D5005 Data Sheet

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ID 683568
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Board Management Controller 4. FPGA Interface Manager 5. System Compatibility 6. Power Requirements 7. Mechanical Information 8. Thermal and Airflow Requirements A. Safety and Regulatory Information B. Revision History
2. Overview x
2.1. Intel® FPGA PAC D5005 Specifications 2.2. Intel® FPGA PAC Components
2.2. Intel® FPGA PAC Components x
2.2.1. Intel® Stratix® 10 FPGA 2.2.2. Power 2.2.3. PCIe* Interface 2.2.4. DDR4 SDRAM 2.2.5. Network Interface 2.2.6. Field Replaceable Unit Identification EEPROM 2.2.7. MAC Address EEPROM 2.2.8. Flash Memory 2.2.9. Control and Support
3. Board Management Controller x
3.1. Health Monitoring Features 3.2. Supported PLDM/MCTP Commands
7. Mechanical Information x
7.1. Ports and LEDs
8. Thermal and Airflow Requirements x
8.1. Thermal Cooling Requirements 8.2. Airflow Requirements
A. Safety and Regulatory Information x
A.1. Regulatory Compliance
1. Introduction
2. Overview
3. Board Management Controller
4. FPGA Interface Manager
5. System Compatibility
6. Power Requirements
7. Mechanical Information
8. Thermal and Airflow Requirements
A. Safety and Regulatory Information
B. Revision History

2.2.2. Power

Given a specific airflow, the Intel® FPGA PAC D5005 can dissipate up to 189 W of power, of which up to 137 W can come from the FPGA. If the airflow is increased, the Intel® FPGA PAC D5005 may be able to dissipate up to 215 W; however, you shall bear the responsibility of thermal validation of these conditions.

The Thermal Design Power (TDP) (215 W) is based on the maximum current, per the PCIe* specification of 5.4 A from the 12 V- PCIe* slot and 12.5 A from the 12 V-Auxiliary 2x4 PCIe* power connector and requires optimized cooling conditions. The card TDP is limited to 189 W under the Thermal and Airflow requirement conditions.

As a developer or solution provider, you must design the AFU to stay within these power guidelines. If the AFU exceeds this limit or the limit provided by the qualified server vendor, Board Management Controller (BMC) safeguards will shut down the Intel® FPGA PAC. Typical server BMC safeguards will likely shut down the server as well. Functionality and reliability of the server and the Intel® FPGA PAC are not supported for AFUs that exceed the specification.

The Intel® FPGA PAC source power must be provided from both the 12 V- PCIe* slot and the 12V-Auxiliary 2x4 power connector.

The Intel® FPGA PAC D5005 is designed to operate under the following conditions:
Table 2.  
Operating Condition Description
No 12 V PCIe slot power, No 12 V Auxiliary Connector Power

Intel® FPGA PAC D5005 OFF

Only 12 V PCIe slot power, No 12 V Auxiliary Connector Power

Intel® FPGA PAC D5005 OFF

No 12 V PCIe Slot Power, only 12 V Auxiliary Connector power available

Intel® FPGA PAC D5005 ON, but limited by the total available power from 12V Aux power connector

12 V PCIe slot power and 12 V Auxiliary Power Connector available

Intel® FPGA PAC D5005 ON, normal operation up to maximum power capabilities of the PAC card design

The 12 V-Auxiliary power connector pin assignment defined by the PCIe* specification is shown below:

Figure 2. Power Connector
Table 3.  2x4 Auxiliary Power Connector Pin-Out Assignment
Pin Signal
1 +12 V
2 +12 V
3 +12 V
4 Sense1
5 Ground
6 Sense0
7 Ground
8 Ground
Level Two Title