Visible to Intel only — GUID: gfn1541113899110
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3. Board Management Controller
A Board Management Controller (BMC) resides on the Intel® FPGA PAC. The BMC is responsible for controlling, monitoring and granting access to board features. The Intel® MAX® 10 BMC interfaces with on-board sensors, the FPGA and the flash, and it controls power-on/power-off sequences, FPGA configuration and telemetry data polling. The BMC communicates using the Platform Level Data Model (PLDM) version 1.1.1 protocol. The BMC firmware is field upgradeable over PCIe* using the remote system update feature.
Features of the BMC
- Interfaces with sensors, FPGA, flash and QSFPs
- FPGA configuration and reconfiguration
- Controls BMC firmware and Intel® Stratix® 10 FPGA flash updates. Updates are provided over PCIe.
- Monitors telemetry data (board temperature, voltage and current) and provides protective action when readings are outside of critical threshold
- Reports telemetry data to host BMC via Platform Level Data Model (PLDM) over MCTP SMBus or Standard I2C
- Supports PLDM over MCTP SMBus via PCIe* SMBus. 0xCE is a 8-bit slave address. Raw 7-bit slave address is 0x67
- Supports Standard I2C via PCIe* SMBus. The I2C slave address is 0xBC (8-bit)
- Intel® FPGA Download Cable functionality for the board
- Power up / down sequencing and fault detection with automatic shut-down protection
- Controls programmable FPGA and DDR4 SDRAM clocks for performance throttling if desired
- Controls power and resets on the board
- Acts as a Root of Trust (RoT) and enables the secure update features of the Intel® FPGA PAC D5005. The RoT includes features that may help prevent the following:
- Loading or executing of unauthorized code or designs.
- Disruptive operations attempted by unprivileged software, privileged software, or the host BMC.
- Unintended execution of older code or designs with known bugs or vulnerabilities by enabling the BMC to revoke authorization.
- Enforces several other security policies relating to access through various interfaces, as well as protecting the on-board flash through write rate limitation.
Refer to the Intel® FPGA PAC D5005 Board Management Controller User Guide for more information.