Intel® FPGA Programmable Acceleration Card D5005 Data Sheet

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ID 683568
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Board Management Controller 4. FPGA Interface Manager 5. System Compatibility 6. Power Requirements 7. Mechanical Information 8. Thermal and Airflow Requirements A. Safety and Regulatory Information B. Revision History
2. Overview x
2.1. Intel® FPGA PAC D5005 Specifications 2.2. Intel® FPGA PAC Components
2.2. Intel® FPGA PAC Components x
2.2.1. Intel® Stratix® 10 FPGA 2.2.2. Power 2.2.3. PCIe* Interface 2.2.4. DDR4 SDRAM 2.2.5. Network Interface 2.2.6. Field Replaceable Unit Identification EEPROM 2.2.7. MAC Address EEPROM 2.2.8. Flash Memory 2.2.9. Control and Support
3. Board Management Controller x
3.1. Health Monitoring Features 3.2. Supported PLDM/MCTP Commands
7. Mechanical Information x
7.1. Ports and LEDs
8. Thermal and Airflow Requirements x
8.1. Thermal Cooling Requirements 8.2. Airflow Requirements
A. Safety and Regulatory Information x
A.1. Regulatory Compliance
1. Introduction
2. Overview
3. Board Management Controller
4. FPGA Interface Manager
5. System Compatibility
6. Power Requirements
7. Mechanical Information
8. Thermal and Airflow Requirements
A. Safety and Regulatory Information
B. Revision History

2.2.4. DDR4 SDRAM

The Intel® FPGA PAC has four banks of Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM). Each bank is populated with 8 GB DDR4 RDIMM modules for a total of 32 GB. The banks are configured as single rank standard RDIMM modules arranged as 72-bit per bank. The memory width is organized as 64 data bits plus 8 ECC bits. Each DDR4 bank operates up to 1200 MHz (DDR4-2400).

Table 5.  Memory Table
Supported Manufacturers Micron
Manufacturer Part Number MTA9ASF1G72PZ-2G9E1
Type 8 GB 288-pin DDR4 RDIMM
Configuration 1 Gb x 72
Rank Single Rank
Error detection and correction (ECC) Yes
Data rate 2400 MT/s
Level Two Title