AN 100: In-System Programmability Guidelines

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ID 683546
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. In-System Programmability Guidelines
1. In-System Programmability Guidelines x
1.1. General ISP Guideline 1.2. IEEE Std. 1149.1 Signals 1.3. Sequential versus Concurrent Programming 1.4. ISP Troubleshooting Guidelines 1.5. ISP through Embedded Processors 1.6. ISP through In-Circuit Testers 1.7. Document Revision History
1.1. General ISP Guideline x
1.1.1. Operating Conditions 1.1.2. User Flash Memory Operations During In-System Programming 1.1.3. Interrupting In-System Programming 1.1.4. MultiVolt Devices and Power-Up Sequences 1.1.5. I/O Pins Tri-Stated During In-System Programming 1.1.6. Pull-Up and Pull-Down of JTAG Pins During In-System Programming
1.1.1. Operating Conditions x
1.1.1.1. ISP Voltage 1.1.1.2. Input Voltages
1.2. IEEE Std. 1149.1 Signals x
1.2.1. TCK Signal 1.2.2. Programming Through a Download Cable 1.2.3. Disabling IEEE Std. 1149.1 Circuitry 1.2.4. Working with Different Voltage Levels
1.3. Sequential versus Concurrent Programming x
1.3.1. Sequential Programming 1.3.2. Concurrent Programming 1.3.3. Selecting Sequential or Concurrent Programming 1.3.4. Devices in Different Modes
1.4. ISP Troubleshooting Guidelines x
1.4.1. Invalid ID and Unrecognized Device Messages 1.4.2. Verify the JTAG Chain Continuity 1.4.3. Check the Voltage Levels of the Board During In-System Programming 1.4.4. Random Signals on JTAG Pins 1.4.5. Software Issues
1.5. ISP through Embedded Processors x
1.5.1. Processor and Memory Requirements 1.5.2. Porting the Jam Player
1. In-System Programmability Guidelines

1.2.1. TCK Signal

A noisy TCK signal causes most in-system programming failures. Noisy transitions on rising or falling edges can cause incorrect clocking of the IEEE Std. 1149.1 TAP controller. Incorrect clocking can cause the state machine to transition to an unknown state, leading to in-system programming failures.

Because the TCK signal must drive all IEEE Std. 1149.1 devices in the chain in parallel, the signal may have a high fan-out. Like any other high fan-out user-mode clock, you must manage a clock tree to maintain signal integrity. Typical errors that result from clock integrity problems are invalid ID messages, blank-check errors, or verification errors.

Altera recommends pulling the TCK signal low through the internal weak pull-down resistor or an external 1-kΩ resistor.

Fast TCK edges combined with board inductance can cause overshoot problems. When this combination occurs, you must either reduce inductance on the trace or reduce the switching rate by selecting a transistor-to-transistor logic (TTL) driver chip with a slower slew rate. You must not use resistor and capacitor networks to slow down edge rates, because resistor and capacitor networks can violate the input specifications of the device. Use a driver chip to prevent the edge rate from being too slow. Altera recommends using driver chips that do not glitch after power up.

Level Two Title