AN 100: In-System Programmability Guidelines

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ID 683546
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. In-System Programmability Guidelines
1. In-System Programmability Guidelines x
1.1. General ISP Guideline 1.2. IEEE Std. 1149.1 Signals 1.3. Sequential versus Concurrent Programming 1.4. ISP Troubleshooting Guidelines 1.5. ISP through Embedded Processors 1.6. ISP through In-Circuit Testers 1.7. Document Revision History
1.1. General ISP Guideline x
1.1.1. Operating Conditions 1.1.2. User Flash Memory Operations During In-System Programming 1.1.3. Interrupting In-System Programming 1.1.4. MultiVolt Devices and Power-Up Sequences VCCINT Powered before VCCIO VCCIO Powered before VCCINT 1.1.5. I/O Pins Tri-Stated During In-System Programming 1.1.6. Pull-Up and Pull-Down of JTAG Pins During In-System Programming
1.1.1. Operating Conditions x
1.1.1.1. ISP Voltage 1.1.1.2. Input Voltages
1.2. IEEE Std. 1149.1 Signals x
1.2.1. TCK Signal 1.2.2. Programming Through a Download Cable 1.2.3. Disabling IEEE Std. 1149.1 Circuitry 1.2.4. Working with Different Voltage Levels
1.3. Sequential versus Concurrent Programming x
1.3.1. Sequential Programming 1.3.2. Concurrent Programming 1.3.3. Selecting Sequential or Concurrent Programming 1.3.4. Devices in Different Modes
1.4. ISP Troubleshooting Guidelines x
1.4.1. Invalid ID and Unrecognized Device Messages 1.4.2. Verify the JTAG Chain Continuity 1.4.3. Check the Voltage Levels of the Board During In-System Programming 1.4.4. Random Signals on JTAG Pins 1.4.5. Software Issues
1.5. ISP through Embedded Processors x
1.5.1. Processor and Memory Requirements 1.5.2. Porting the Jam Player
1. In-System Programmability Guidelines

1.1.4. MultiVolt Devices and Power-Up Sequences

For the JTAG circuitry to operate correctly during in-system programming or boundary-scan testing, all devices in a JTAG chain must be in the same state. If you do not hold the JTAG pins in the test-logic-reset state, in-system programming errors can occur.

Therefore, in systems with multiple power supply voltages, you must hold the JTAG pins in the test-logic-reset state until all devices in the chain are fully powered up. This procedure is important because systems that have multiple power supplies cannot power all voltage levels simultaneously.

MAX devices have the MultiVolt™ feature and can use more than one power supply voltage:

  • MAX 10 devices—VCC/VCC_ONE provides power to core and periphery, VCCIO provides power to input pins and output buffer, and VCCA provides power to PLL regulator.
  • Other MAX devices—VCCINT and VCCIO for each I/O bank. VCCINT provides power to the JTAG circuitry; VCCIO provides power to input pins and output drivers for output pins, including TDO pin.

VCCINT Powered before VCCIO

If VCCINT is powered up before VCCIO, the JTAG circuitry is active but unable to drive out signals. Thus, any transition on the TCK pin can cause the state machine to transition to an unknown JTAG state. If TMS and TCK pins are connected to VCCIO and VCCIO is not powered up, the JTAG signals are left floating. These floating values can cause the device to transition to unintended JTAG states, leading to incorrect operation when VCCIO is finally powered up. Therefore, you must disable all JTAG signals.

VCCIO Powered before VCCINT

If VCCIO is powered up before VCCINT, the JTAG circuitry is not active but the TDO pin is tri-stated. Although the JTAG circuitry is not active and if the next device in the JTAG chain is powered up with the same trace as VCCIO, its JTAG circuitry must stay in the test-logic-reset state. Because all TMS and TCK signals are common, you must disable these signals for all devices in the chain. Therefore, you must disable the JTAG pins by pulling the TCK signal low and the TMS signal high. With the MAX 10 device hot-socketing feature, you no longer need to ensure a proper power up sequence for each device on the board.

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