AN 100: In-System Programmability Guidelines

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ID 683546
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. In-System Programmability Guidelines
1. In-System Programmability Guidelines x
1.1. General ISP Guideline 1.2. IEEE Std. 1149.1 Signals 1.3. Sequential versus Concurrent Programming 1.4. ISP Troubleshooting Guidelines 1.5. ISP through Embedded Processors 1.6. ISP through In-Circuit Testers 1.7. Document Revision History
1.1. General ISP Guideline x
1.1.1. Operating Conditions 1.1.2. User Flash Memory Operations During In-System Programming 1.1.3. Interrupting In-System Programming 1.1.4. MultiVolt Devices and Power-Up Sequences 1.1.5. I/O Pins Tri-Stated During In-System Programming 1.1.6. Pull-Up and Pull-Down of JTAG Pins During In-System Programming
1.1.1. Operating Conditions x
1.1.1.1. ISP Voltage 1.1.1.2. Input Voltages
1.2. IEEE Std. 1149.1 Signals x
1.2.1. TCK Signal 1.2.2. Programming Through a Download Cable 1.2.3. Disabling IEEE Std. 1149.1 Circuitry 1.2.4. Working with Different Voltage Levels
1.3. Sequential versus Concurrent Programming x
1.3.1. Sequential Programming 1.3.2. Concurrent Programming 1.3.3. Selecting Sequential or Concurrent Programming 1.3.4. Devices in Different Modes
1.4. ISP Troubleshooting Guidelines x
1.4.1. Invalid ID and Unrecognized Device Messages 1.4.2. Verify the JTAG Chain Continuity 1.4.3. Check the Voltage Levels of the Board During In-System Programming 1.4.4. Random Signals on JTAG Pins 1.4.5. Software Issues
1.5. ISP through Embedded Processors x
1.5.1. Processor and Memory Requirements 1.5.2. Porting the Jam Player
1. In-System Programmability Guidelines

1.1.5. I/O Pins Tri-Stated During In-System Programming

By default, all device I/O pins are tri-stated during in-system programming. In addition, MAX devices provide a weak pull-up resistor during ISP. The purpose of this weak pull-up resistor is to eliminate the requirement for external pull-up resistors on tri-stated I/O pins.

You must add sufficient pull-up or pull-down resistors on signals that require a particular value during in-system programming (for example, JTAG configuration signals). If a pull-up or pull-down resistor is not added, the device could have high current during in-system programming (caused by conflicts on the board), in-system programming failures with either unrecognized device or verify errors, or a power up after in-system programming fails.

For MAX II, MAX V and MAX 10 devices, you can use the in-system programming clamp feature or the real-time ISP feature to ensure that each I/O pin is clamped to a specific state during in-system programming.

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