Visible to Intel only — GUID: nik1412473923794
Ixiasoft
1.1. Understanding Throughput in PCI Express
1.2. Deliverables Included with the Reference Design
1.3. Reference Design Functional Description
1.4. Hardware Requirements
1.5. Software Requirements
1.6. Software Installation
1.7. Hardware Installation
1.8. Running the Software Application
1.9. Additional Chaining DMA Commands
1.10. Using SignalTap II
1.11. Performance Benchmarking Results
1.12. Document Revision History
Visible to Intel only — GUID: nik1412473923794
Ixiasoft
1.10. Using SignalTap II
The reference design package also includes .stp files. The SignalTap II file can provide information on the performance of this design. The SignalTap II file includes the key signals from the application logic. The init signal in the DMA read and write modules transitions to zero at the beginning of the transfer. You can use the init signal as a trigger in the SignalTap II file to capture data.
The tx_st_ready0 and rx_st_valid0 are indications of link utilization and throughput. In the transmit direction, the frequent deassertion of the tx_st_ready0 signal typically indicates that the IP core is not receiving enough credits from the device at the far end of the PCI Express link. It could also indicate that a x4 link has trained to x1. In the receive direction, the deassertion of rx_st_valid0 indicates that the IP core is not receiving enough data.