AN 456: PCI Express High Performance Reference Design

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ID 683541
Date 12/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. File Naming Conventions 1.3.2. Project Hierarchy
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.9. Additional Chaining DMA Commands

In addition to the parameter settings to control the chaining DMA, the GUI includes five other commands. The following table describes these commands. The position of the slider control changes the command.
Table 6.  PCI Express Performance Demo GUI Commands and Options
Command Options Description
Run endpoint DMA Write only
Read only
Read then write
Write then read
Read and write Writes transfers data from the FPGA to system memory. Reads transfer data from system memory to the FPGA.
Scan the endpoint configuration space registers Type 0 Configuration
PCI Express capability
MSI capability
Power management capability Reports the byte address offset, value and a description of the selected register set.
Scan the current PCI Express board settings N/A Reports the configuration settings for the development board.
Scan the motherboard PCI bus N/A Reports the vendor ID, device ID, slot, bus, and function numbers for all devices on the motherboard’s PCI bus.
Run target read At endpoint address
From 0x0 to endpoint address Programs the Root Port of the motherboard’s PCI Express chipset to read from the FPGA’s memory, as follows:
  • If you select At Endpoint address, you can type the starting read address in Endpoint memory in the Endpoint address field.
  • If you select From 0x0 to Endpoint address, the Endpoint address field specifies the transfer length.
Run target write At endpoint address
From 0x0 to endpoint address Programs the Root Port of the motherboard’s PCI Express chipset to write to the FPGA’s memory, as follows:
  • If you select At Endpoint address, you can type the starting write address in Endpoint memory the Endpoint address field.
  • If you select From 0x0 to Endpoint address, the Endpoint address field specifies the transfer length.
Figure 8. Scan the Endpoint Configuration Space Registers
Figure 9. Scan the current PCI Express Board Settings
Level Two Title