1.3.2. Project Hierarchy
The directory structure used for the Arria V, Cyclone V, and Stratix V reference design differs from the earlier device families.
Arria V, Cyclone V, and Stratix V Directory Structure
Arria V, Cyclone V, and Stratix V devices use the following directory structure:
- top—the project directory. The top-level entity is top_example_chaining_top.
- pcie_lib—includes all design files. If you modify the design, you must copy the modified files to the pcie_lib directory before recompiling the design.
Arria II GX, Cyclone IV GX, and Stratix IV GX Directory Structure
These devices use the following directory structure:
- top or top_ <n> gx—top is the top-level project directory for the hard IP implementation. The soft IP implementation may have a <n> gx suffix where <n> indicates the number of lanes. In both cases, the top-level entity is top_example_chaining_top.
- top_examples/chaining_dma—includes design files to implement the chaining DMA.
- ip_compiler_for_pci_express—includes library files for PCI Express.
IP Core Settings
The reference design supports a maximum payload size of 512 Bytes. The desired performance for received completions and requests is set to Maximum. The following tables show the settings for supported devices.
Parameter | Value |
---|---|
PCIe IP core type | PCI Express hard IP |
PCIe System Parameters | |
PHY type | Stratix V GX |
PHY interface | Serial |
System Settings | |
Number of lanes | x8 |
Lane rate | Gen2 (5.0 Gbps) |
Port type | Native endpoint |
PCI Express Base Specification version | 2.1 |
Application interface | Avalon-ST 128-bit |
RX buffer credit allocation | Low |
Reference clock frequency | 100 MHz |
Use 62.5 MHz application clock | OFF |
Use deprecated RX Avalon-ST data byte enable port(rx_st_be) | ON |
Enable byte parity ports on Avalon-ST interface | OFF |
Enable multiple packets per cycle | OFF |
Enable configuration via the PCIe link | OFF |
Use credit consumed selection port tx_cons_cred_sel | OFF |
Enable Configuration Bypass | OFF |
Enable Hard IP reconfiguration | OFF |
PCI Base Address Registers (Type 0 Configuration Space) | ||
---|---|---|
BAR | BAR Type | BAR Size |
0 | 32-bit Non-Prefetchable Memory | 256 MBytes - 28 bits |
1 | Disabled | N/A |
2 | 32-bit Non-Prefetchable Memory | 1 KBytes - 10 bits |
Base and Limit Registers for Root Ports | ||
Input/Output | Disabled | |
Prefetchable memory | Disabled | |
PCI Read-Only Registers | ||
Register Name | Value | Additional Information |
Vendor ID | 0x1172 | The Vendor ID can be either 0x1172 or 0xB0D8. This parameter has no effect on design behavior. |
Device ID | 0xE001 | N/A |
Revision ID | 0x1 | N/A |
Class Code | 0x00FF0000 | N/A |
Subsystem Vendor ID | 0xA8 | For this design, theSubsystem Vendor ID is the encoded value used by the GUI to identify the device family and configuration. Consequently, it changes depending on the settings specified. |
Subsystem Device ID | 0x2801 | N/A |
Capability Registers | |
---|---|
Device Capabilities | |
Maximum payload size | 256 Bytes |
Number of tags supported | 32 |
Completion timeout range | ABCD |
Implement completion timeout disable | ON |
Error Reporting | |
Advanced error reporting (AER) | Off |
ECRC check | Off |
ECRC generation | Off |
ECRC forwarding | Off |
Track receive completion buffer overflow | Off |
Link Capabilities | |
Link port number | 1 |
Data link layer active reporting | Off |
Surprise down reporting | Off |
Slot clock configuration | On |
MSI Capabilities | |
MSI messages requested | 4 |
MSI-X Capabilities | |
Implement MSI-X | Off |
MSI-X Table size | 0 |
MSI-X Table Offset | 0x0 |
MSI-X Table BAR Indicator (BIR) | 1 |
Pending Bit Array (PBA) | 0x0 |
Offset | 0 |
BAR Indicator | 0 |
Slot Capabilities | |
Use slot register | Off |
Slot power scale | 0 |
Slot power limit | 0 |
Slot number | 0 |
Parameter | Value |
---|---|
Power Management | |
Endpoint L0s acceptable latency | Maximum of 64 ns |
Endpoint L1 acceptable latency | Maximum of 1 us |
PHY Characteristics | |
Gen2 transmit deemphasis | 6dB |
Quartus II Settings
The .qar files in the reference design package has the recommended synthesis, Fitter, and timing analysis settings. These settings are optimized for the parameters chosen in this reference design.