Visible to Intel only — GUID: ulp1512684708279
Ixiasoft
Visible to Intel only — GUID: ulp1512684708279
Ixiasoft
1.1.2. Memory Address Mapping
The PCIe* IP core connects to the design core through two BARs (base address registers) - BAR 2 and BAR 4, which in turn connect to their exclusive Avalon-MM interface.
Domain | Address Map | Base | End |
---|---|---|---|
BAR 2 | System Description ROM | 0x0000_0000 | 0x0000_0FFF |
BAR 2 | PR IP | 0x0000_1000 | 0x0000_103F |
BAR 4 | PR Region | 0x0000_0000 | 0x0000_FFFF |
BAR 4 | PR Region Controller | 0x0001_0000 | 0x0001_000F |
BAR 4 | DDR4 Calibration Export | 0x0001_0010 | 0x0001_001F |
The reference design exports the status of the DDR4 calibration, provided by the External Memory Interfaces IP core. Upon initialization, the EMIF IP core performs training to reset the DDR4 interface. The EMIF reports the success or the failure of the reset in its calibration flag. The host decides the necessary action in the event of DDR4 failing the reset training, so this interface is exported to the host.
The following table lists the memory address mapping from the External Memory Interfaces IP core, to the PR logic:Address Map | Base | End |
---|---|---|
DDR | 0x0000_0000 | 0x7fff_ffff |